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Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko , Axel Rasmussen , Yuanchu Xie , Chunyan Zhang Subject: Re: [PATCH V12 3/5] riscv: Add RISC-V Svrsw60t59b extension support Message-ID: References: <20250915101343.1449546-1-zhangchunyan@iscas.ac.cn> <20250915101343.1449546-4-zhangchunyan@iscas.ac.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20250915101343.1449546-4-zhangchunyan@iscas.ac.cn> X-Rspamd-Queue-Id: 13AC34000D X-Rspamd-Server: rspam05 X-Stat-Signature: jy71ifojygw9arexmxbw935hdaqg5r64 X-Rspam-User: X-HE-Tag: 1758059854-472318 X-HE-Meta: U2FsdGVkX1+YJy38d1+z36XHETaK+NbaJpOPj8pPEIxwdApKYjVzb1lUm0bRhaIFu8C9XPQZ4Yx6GaYUvGIvQZmSEgQ9OIL9lh+NdE6Kk8MldUbOjLiAWdeIiU4fOSVJSvZVlrh1Y2WpYFSs/y+g8V5cs5D9YMSuOM7+Kmj696ryWN46/PQQr65NO135xSLo/dNnv4mi14Rkbt04e8kgOODwSLh1rNxFMaRh+COvnckfVeQR5gYkbknfsW4IqZrQGSfQMsjpsWHyANCsjB0kMECIYvrUs2xUcmQfAgts2qDDO/1wh9eo2arPqgt7DRBaq1xSOp421Hn/KVQTqaUsjp6Dq1rX87Dozf53KePndwkUO30jjQ+/C/Q3QWi/qFTClvXQ/08TPFxcWiCNT733aL8MjbDjszO2Yta7SZDrOSx7X3cx7JZLuvwh0DNFlXbAHEqHiNBiyWqDpLNuheyteXTnPzfkdBVo3+MubfI7CdT7x1KP4skY6QD5vVsw/7/L8kBeiegur35/0OxQghMi54FjipMjRlkL/EQjPiFKzUTIdzA+7WZLznqZbBHzsn+5cb+P3sLhitZKtoBJXs2fkAwbJPhYUoKBck0qQwCmdxixt4rdw0oaj0PcKRHN7j9L+Ckv9OR9AWO0t3zoo2cZ/QKiwNk9wERog+rUHr6NX92eHW+lTcDpvhGaah60EeTUUr2ld8XLlXe3OzRqKwiK3lR/XFrqWO1n34jugt8VY3pVscvpItm+BeOom9WWQu2++rGngODcS2LD9rSrHHiO8nLMMehmHq6AtFaHNtEfqBPUAIayvDMELKlkb2geKdtf4z+OF0zS5irpve+XdPhJnNUgzQY6579BzlJAyaNer8tf4qehAFGtRSDOD8aeoS7yCGxYzXTmyXqSFJWMO4VorR/Rl3tYihQ+wApK4IN7YhBzEOKCZ99hllsk2vv61SCmIkHelG2TU0DhwiT0YYm aZIQ2xl0 LDVjCE++nPWTZDFxTjbTQ0OnbWc1U3EzVoYkCMSz+iRGMioDEgHaA4eGvE3N5rwTz4sfZs/tbfffLFzPpaD4XPf8ak+uMjaZB+hvZ X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Mon, Sep 15, 2025 at 06:13:41PM +0800, Chunyan Zhang wrote: >The Svrsw60t59b extension allows to free the PTE reserved bits 60 >and 59 for software to use. > >Reviewed-by: Alexandre Ghiti >Reviewed-by: Andrew Jones >Signed-off-by: Chunyan Zhang Same comment as Conor for dt-bindings. Other than that Reviewed-by: Deepak Gupta >--- > arch/riscv/Kconfig | 14 ++++++++++++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 3 files changed, 16 insertions(+) > >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >index 51dcd8eaa243..e1b6a95952c4 100644 >--- a/arch/riscv/Kconfig >+++ b/arch/riscv/Kconfig >@@ -862,6 +862,20 @@ config RISCV_ISA_ZICBOP > > If you don't know what to do here, say Y. > >+config RISCV_ISA_SVRSW60T59B >+ bool "Svrsw60t59b extension support for using PTE bits 60 and 59" >+ depends on MMU && 64BIT >+ depends on RISCV_ALTERNATIVE >+ default y >+ help >+ Adds support to dynamically detect the presence of the Svrsw60t59b >+ extension and enable its usage. >+ >+ The Svrsw60t59b extension allows to free the PTE reserved bits 60 >+ and 59 for software to use. >+ >+ If you don't know what to do here, say Y. >+ > config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI > def_bool y > # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc >diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >index affd63e11b0a..f98fcb5c17d5 100644 >--- a/arch/riscv/include/asm/hwcap.h >+++ b/arch/riscv/include/asm/hwcap.h >@@ -106,6 +106,7 @@ > #define RISCV_ISA_EXT_ZAAMO 97 > #define RISCV_ISA_EXT_ZALRSC 98 > #define RISCV_ISA_EXT_ZICBOP 99 >+#define RISCV_ISA_EXT_SVRSW60T59B 100 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > >diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >index 743d53415572..2ba71d2d3fa3 100644 >--- a/arch/riscv/kernel/cpufeature.c >+++ b/arch/riscv/kernel/cpufeature.c >@@ -539,6 +539,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), >+ __RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B), > __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), > }; 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Tue, 16 Sep 2025 14:57:33 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-32ea3c72dacsm1636848a91.4.2025.09.16.14.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 14:57:33 -0700 (PDT) Date: Tue, 16 Sep 2025 14:57:31 -0700 From: Deepak Gupta To: Chunyan Zhang Cc: linux-riscv@lists.infradead.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ved Shanbhogue , Alexander Viro , Christian Brauner , Jan Kara , Andrew Morton , Peter Xu , Arnd Bergmann , David Hildenbrand , Lorenzo Stoakes , "Liam R . Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko , Axel Rasmussen , Yuanchu Xie , Chunyan Zhang Subject: Re: [PATCH V12 3/5] riscv: Add RISC-V Svrsw60t59b extension support Message-ID: References: <20250915101343.1449546-1-zhangchunyan@iscas.ac.cn> <20250915101343.1449546-4-zhangchunyan@iscas.ac.cn> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250915101343.1449546-4-zhangchunyan@iscas.ac.cn> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250916_145734_675110_FB2E336E X-CRM114-Status: GOOD ( 12.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Sep 15, 2025 at 06:13:41PM +0800, Chunyan Zhang wrote: >The Svrsw60t59b extension allows to free the PTE reserved bits 60 >and 59 for software to use. > >Reviewed-by: Alexandre Ghiti >Reviewed-by: Andrew Jones >Signed-off-by: Chunyan Zhang Same comment as Conor for dt-bindings. Other than that Reviewed-by: Deepak Gupta >--- > arch/riscv/Kconfig | 14 ++++++++++++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 3 files changed, 16 insertions(+) > >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >index 51dcd8eaa243..e1b6a95952c4 100644 >--- a/arch/riscv/Kconfig >+++ b/arch/riscv/Kconfig >@@ -862,6 +862,20 @@ config RISCV_ISA_ZICBOP > > If you don't know what to do here, say Y. > >+config RISCV_ISA_SVRSW60T59B >+ bool "Svrsw60t59b extension support for using PTE bits 60 and 59" >+ depends on MMU && 64BIT >+ depends on RISCV_ALTERNATIVE >+ default y >+ help >+ Adds support to dynamically detect the presence of the Svrsw60t59b >+ extension and enable its usage. >+ >+ The Svrsw60t59b extension allows to free the PTE reserved bits 60 >+ and 59 for software to use. >+ >+ If you don't know what to do here, say Y. >+ > config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI > def_bool y > # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc >diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >index affd63e11b0a..f98fcb5c17d5 100644 >--- a/arch/riscv/include/asm/hwcap.h >+++ b/arch/riscv/include/asm/hwcap.h >@@ -106,6 +106,7 @@ > #define RISCV_ISA_EXT_ZAAMO 97 > #define RISCV_ISA_EXT_ZALRSC 98 > #define RISCV_ISA_EXT_ZICBOP 99 >+#define RISCV_ISA_EXT_SVRSW60T59B 100 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > >diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >index 743d53415572..2ba71d2d3fa3 100644 >--- a/arch/riscv/kernel/cpufeature.c >+++ b/arch/riscv/kernel/cpufeature.c >@@ -539,6 +539,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), >+ __RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B), > __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), > }; > >-- >2.34.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv