From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Andrew Lunn <andrew@lunn.ch>
Cc: netdev@vger.kernel.org, Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Richard Cochran <richardcochran@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>
Subject: Re: [PATCH RFC net-next 03/20] net: phy: marvell: add PHY PTP support
Date: Thu, 18 Sep 2025 21:33:27 +0100 [thread overview]
Message-ID: <aMxsl4v-Aio6R20R@shell.armlinux.org.uk> (raw)
In-Reply-To: <299f61cc-b5a7-48a6-b16d-f1f5d639af85@lunn.ch>
On Thu, Sep 18, 2025 at 10:12:02PM +0200, Andrew Lunn wrote:
> > +static u64 marvell_phy_tai_clock_read(struct device *dev,
> > + struct ptp_system_timestamp *sts)
> > +{
> > + struct phy_device *phydev = to_phy_device(dev);
> > + int err, oldpage, lo, hi;
> > +
> > + oldpage = phy_select_page(phydev, MARVELL_PAGE_PTP_GLOBAL);
> > + if (oldpage >= 0) {
> > + /* 88e151x says to write 0x8e0e */
> > + ptp_read_system_prets(sts);
> > + err = __phy_write(phydev, PTPG_READPLUS_COMMAND, 0x8e0e);
> > + ptp_read_system_postts(sts);
> > + lo = __phy_read(phydev, PTPG_READPLUS_DATA);
> > + hi = __phy_read(phydev, PTPG_READPLUS_DATA);
> > + }
> > + err = phy_restore_page(phydev, oldpage, err);
> > +
> > + if (err || lo < 0 || hi < 0)
> > + return 0;
> > +
> > + return lo | hi << 16;
>
> What happens when hi is >= 0x8000? Doesn't that result in undefined
> behaviour for 32 bit machines? The u64 result we are trying to return
> is big enough to hold the value. Does the hi need promoting to u64
> before doing the shift?
Good point - looking at the generated code, it gets sign-extended
to a 64 bit value. So, hi=0x8000 results in 0xffffffff8000XXXX
being returned.
Does it matter? There are two functions that call the cyclecounter
->read() method. timecounter_init() sets ->cycle_last from the
value, and timecounter_read_delta() does this:
cycle_delta = (cycle_now - tc->cycle_last) & tc->cc->mask;
before updating ->cycle_last with the returned value. As the
mask is initialised thusly:
tai->cyclecounter.mask = CYCLECOUNTER_MASK(32);
this masks off the sign-extended high 32-bits, giving us back
a value of 0x8000XXXX.
So, while the sign extension is undesirable, it has no effect on
the operation. Is it worth throwing casts in the code? I suspect
that's a matter of personal opinion.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
next prev parent reply other threads:[~2025-09-18 20:33 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-18 17:38 [PATCH RFC net-next 00/20] Marvell PTP stuffs Russell King (Oracle)
2025-09-18 17:38 ` [PATCH RFC net-next 01/20] ptp: marvell: add core support for Marvell PTP Russell King
2025-09-18 17:39 ` [PATCH RFC net-next 02/20] net: phy: add hwtstamp_get() method for mii timestampers Russell King (Oracle)
2025-09-18 20:38 ` Andrew Lunn
2025-09-18 17:39 ` [PATCH RFC net-next 03/20] net: phy: marvell: add PHY PTP support Russell King
2025-09-18 20:12 ` Andrew Lunn
2025-09-18 20:33 ` Russell King (Oracle) [this message]
2025-09-19 1:47 ` Andrew Lunn
2025-09-18 17:39 ` [PATCH RFC net-next 04/20] net: dsa: mv88e6xxx: split out set_ptp_cpu_port() code Russell King (Oracle)
2025-09-18 20:46 ` Andrew Lunn
2025-09-18 17:39 ` [PATCH RFC net-next 05/20] net: dsa: mv88e6xxx: convert PTP clock_read() method to take chip Russell King (Oracle)
2025-09-18 20:13 ` Andrew Lunn
2025-09-18 17:39 ` [PATCH RFC net-next 06/20] net: dsa: mv88e6xxx: convert PTP ptp_verify() " Russell King (Oracle)
2025-09-18 20:48 ` Andrew Lunn
2025-09-18 17:39 ` [PATCH RFC net-next 07/20] net: dsa: mv88e6xxx: convert PTP ptp_enable() " Russell King (Oracle)
2025-09-18 20:48 ` Andrew Lunn
2025-09-18 17:39 ` [PATCH RFC net-next 08/20] net: dsa: mv88e6xxx: convert mv88e6xxx_hwtstamp_work() " Russell King (Oracle)
2025-09-18 20:51 ` Andrew Lunn
2025-09-18 17:39 ` [PATCH RFC net-next 09/20] net: dsa: mv88e6xxx: always verify PTP_PF_NONE Russell King (Oracle)
2025-09-18 20:14 ` Andrew Lunn
2025-09-18 17:39 ` [PATCH RFC net-next 10/20] net: dsa: mv88e6xxx: only support EXTTS for pins Russell King (Oracle)
2025-09-19 11:29 ` Vadim Fedorenko
2025-09-19 13:50 ` Russell King (Oracle)
2025-09-18 17:39 ` [PATCH RFC net-next 11/20] net: dsa: mv88e6xxx: split out EXTTS pin setup Russell King (Oracle)
2025-09-18 20:59 ` Andrew Lunn
2025-09-28 9:51 ` Russell King (Oracle)
2025-09-18 17:39 ` [PATCH RFC net-next 12/20] net: dsa: mv88e6xxx: move EXTTS flag validation and pin lookup Russell King (Oracle)
2025-09-18 17:39 ` [PATCH RFC net-next 13/20] net: dsa: mv88e6xxx: convert to marvell TAI Russell King (Oracle)
2025-09-18 17:40 ` [PATCH RFC net-next 14/20] net: dsa: mv88e6xxx: convert mv88e6xxx_cc_coeffs to marvell_tai_param Russell King (Oracle)
2025-09-18 17:40 ` [PATCH RFC net-next 15/20] net: dsa: mv88e6xxx: allow generic core to configure global regs Russell King (Oracle)
2025-09-18 17:40 ` [PATCH RFC net-next 16/20] net: dsa: mv88e6xxx: add beginnings of generic Marvell PTP ts layer Russell King (Oracle)
2025-09-18 17:40 ` [PATCH RFC net-next 17/20] net: dsa: mv88e6xxx: switch tx timestamping to core Russell King (Oracle)
2025-09-18 17:40 ` [PATCH RFC net-next 18/20] net: dsa: mv88e6xxx: switch rx " Russell King (Oracle)
2025-09-18 17:40 ` [PATCH RFC net-next 19/20] net: dsa: mv88e6xxx: switch hwtstamp config to core XXX Fix 6165 Russell King (Oracle)
2025-09-18 17:40 ` [PATCH RFC net-next 20/20] net: dsa: mv88e6xxx: add ptp irq support Russell King (Oracle)
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