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[213.67.3.247]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-373ba274b6fsm4962731fa.5.2025.10.02.00.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 00:33:59 -0700 (PDT) Date: Thu, 2 Oct 2025 09:33:58 +0200 From: "Edgar E. Iglesias" To: =?iso-8859-1?Q?Cl=E9ment?= Chigot Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, alistair@alistair23.me Subject: Re: [PATCH 1/3] hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in header Message-ID: References: <20250930115718.437100-1-chigot@adacore.com> <20250930115718.437100-2-chigot@adacore.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250930115718.437100-2-chigot@adacore.com> User-Agent: Mutt/2.2.14+84 (2efcabc4) (2025-03-23) Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Tue, Sep 30, 2025 at 01:57:16PM +0200, Clément Chigot wrote: > This define will be needed in a later patch in XlnxZynqMPState > structure, hence move it within xlnx-zynqmp header. > > Add XLXN_ZYNQMP prefix as it's now public. > > Signed-off-by: Clément Chigot Reviewed-by: Edgar E. Iglesias > --- > hw/arm/xlnx-zynqmp.c | 11 +++++------ > include/hw/arm/xlnx-zynqmp.h | 1 + > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c > index ec96a46eec..d7adc070f8 100644 > --- a/hw/arm/xlnx-zynqmp.c > +++ b/hw/arm/xlnx-zynqmp.c > @@ -26,8 +26,6 @@ > #include "target/arm/cpu-qom.h" > #include "target/arm/gtimer.h" > > -#define GIC_NUM_SPI_INTR 160 > - > #define ARM_PHYS_TIMER_PPI 30 > #define ARM_VIRT_TIMER_PPI 27 > #define ARM_HYP_TIMER_PPI 26 > @@ -206,7 +204,7 @@ static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { > > static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) > { > - return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; > + return XLNX_ZYNQMP_GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; > } > > static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, > @@ -454,7 +452,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); > const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; > ram_addr_t ddr_low_size, ddr_high_size; > - qemu_irq gic_spi[GIC_NUM_SPI_INTR]; > + qemu_irq gic_spi[XLNX_ZYNQMP_GIC_NUM_SPI_INTR]; > Error *err = NULL; > > ram_size = memory_region_size(s->ddr_ram); > @@ -502,7 +500,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > g_free(ocm_name); > } > > - qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); > + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", > + XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32); > qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); > qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); > qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); > @@ -613,7 +612,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > return; > } > > - for (i = 0; i < GIC_NUM_SPI_INTR; i++) { > + for (i = 0; i < XLNX_ZYNQMP_GIC_NUM_SPI_INTR; i++) { > gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); > } > > diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h > index c137ac59e8..6a407c2962 100644 > --- a/include/hw/arm/xlnx-zynqmp.h > +++ b/include/hw/arm/xlnx-zynqmp.h > @@ -67,6 +67,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) > #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 > > #define XLNX_ZYNQMP_GIC_REGIONS 6 > +#define XLNX_ZYNQMP_GIC_NUM_SPI_INTR 160 > > /* > * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets > -- > 2.34.1 >