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d="scan'208";a="180851305" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.115]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2025 03:07:49 -0700 Date: Mon, 22 Sep 2025 13:07:45 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Ankit Nautiyal Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: Re: [PATCH 3/9] drm/i915/display: Use VBLANK_START to get the vblank delay for TGL Message-ID: References: <20250921043535.2012978-1-ankit.k.nautiyal@intel.com> <20250921043535.2012978-4-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250921043535.2012978-4-ankit.k.nautiyal@intel.com> X-Patchwork-Hint: comment Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Sun, Sep 21, 2025 at 10:05:29AM +0530, Ankit Nautiyal wrote: > For TGL the TRANS_SET_CONTEXT_LATENCY doesn't exist to account for SCL. > However, the VBLANK_START-VACTIVE diffence plays an identical role here ie. > it can be used to create the SCL window ahead of the undelayed vblank. > > While readback there is no specific register to read out the SCL, so use > the same helper intel_crtc_compute_scl() and reduce the vblank_start by > this amount. > > Signed-off-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 5a7794387ea2..455bbebb50a5 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2822,6 +2822,16 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, > adjusted_mode->crtc_vblank_end += 1; > } > > + if (DISPLAY_VER(display) == 12) { > + /* > + * There is no specific register for SCL for TGL. > + * Derive the value from the helper intel_crtc_set_context_latency(). > + * crtc_vblank_start needs to be reduced with this amount. > + */ > + pipe_config->set_context_latency = intel_crtc_set_context_latency(pipe_config); That thing *computes* the SCL, it doesn't teel us what the current hw value is. > + adjusted_mode->crtc_vblank_start -= pipe_config->set_context_latency; > + } > + > if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) { > pipe_config->set_context_latency = > intel_de_read(display, I think this whole thing needs to look something like this: if (DISPLAY_VER >= 13 && !dsi) { set_context_latency = read(TRANS_SET_CONTEXT_LATENCY); crtc_vblank_start = crtc_vdisplay + set_set_context_latency; } else if (DISPLAY_VER >= 12) { set_context_latency = crtc_vblank_start - crtc_vdisplay; } That'll also cover DSI (not that the DSI code itself is actually ready for SCL...). And I think you need to squash this into the set_context_latency patch. Otherwise we'll get state checker mismatches on TGL in between. -- Ville Syrjälä Intel