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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 10/10] drm/i915/dsb: Inline dsb_vblank_delay() into intel_dsb_wait_for_delayed_vblank()
Date: Wed, 24 Sep 2025 18:20:30 +0300	[thread overview]
Message-ID: <aNQMPqBkts5HKQa3@intel.com> (raw)
In-Reply-To: <20250924141542.3122126-11-ankit.k.nautiyal@intel.com>

On Wed, Sep 24, 2025 at 07:45:42PM +0530, Ankit Nautiyal wrote:
> Drop the now single-use dsb_vblank_delay() helper and inline its logic
> directly into intel_dsb_wait_for_delayed_vblank().
> 
> This will help to keep all VRR related wait stuff in one place.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 56 ++++++++++--------------
>  1 file changed, 24 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index ae8574880ef2..44a465ff52d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -115,24 +115,6 @@ static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
>  	return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc);
>  }
>  
> -static int dsb_vblank_delay(struct intel_atomic_state *state,
> -			    struct intel_crtc *crtc)
> -{
> -	const struct intel_crtc_state *crtc_state =
> -		intel_pre_commit_crtc_state(state, crtc);
> -
> -	if (pre_commit_is_vrr_active(state, crtc))
> -		/*
> -		 * When the push is sent during vblank it will trigger
> -		 * on the next scanline, hence we have up to one extra
> -		 * scanline until the delayed vblank occurs after
> -		 * TRANS_PUSH has been written.
> -		 */
> -		return crtc_state->set_context_latency + 1;
> -	else
> -		return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
> -}
> -
>  static int dsb_vtotal(struct intel_atomic_state *state,
>  		      struct intel_crtc *crtc)
>  {
> @@ -821,24 +803,34 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
>  	struct intel_crtc *crtc = dsb->crtc;
>  	const struct intel_crtc_state *crtc_state =
>  		intel_pre_commit_crtc_state(state, crtc);
> -	int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
> -					     dsb_vblank_delay(state, crtc));
> +	int usecs;
>  
> -	/*
> -	 * If the push happened before the vmin decision boundary
> -	 * we don't know how far we are from the undelayed vblank.
> -	 * Wait until we're past the vmin safe window, at which
> -	 * point we're SCL lines away from the delayed vblank.
> -	 *
> -	 * If the push happened after the vmin decision boundary
> -	 * the hardware itself guarantees that we're SCL lines
> -	 * away from the delayed vblank, and we won't be inside
> -	 * the vmin safe window so this extra wait does nothing.
> -	 */
> -	if (pre_commit_is_vrr_active(state, crtc))
> +	if (pre_commit_is_vrr_active(state, crtc)) {
> +		/*
> +		 * If the push happened before the vmin decision boundary
> +		 * we don't know how far we are from the undelayed vblank.
> +		 * Wait until we're past the vmin safe window, at which
> +		 * point we're SCL lines away from the delayed vblank.
> +		 *
> +		 * If the push happened after the vmin decision boundary
> +		 * the hardware itself guarantees that we're SCL lines
> +		 * away from the delayed vblank, and we won't be inside
> +		 * the vmin safe window so this extra wait does nothing.
> +		 */
>  		intel_dsb_wait_scanline_out(state, dsb,
>  					    intel_vrr_safe_window_start(crtc_state),
>  					    intel_vrr_vmin_safe_window_end(crtc_state));
> +		/*
> +		 * When the push is sent during vblank it will trigger
> +		 * on the next scanline, hence we have up to one extra
> +		 * scanline until the delayed vblank occurs after
> +		 * TRANS_PUSH has been written.
> +		 */
> +		usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
> +						 crtc_state->set_context_latency + 1);
> +	} else {
> +		usecs = intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);

That also returns the delay in scanlines.

> +	}
>  
>  	intel_dsb_wait_usec(dsb, usecs);

So I guess just do the scanline_to_usec() conversion here when calling
wait_usec().

I think eventually we may want to change this part to be:

if (something)
	intel_dsb_wait_hblanks(x);
else
	intel_dsb_wait_usec(intel_scanlines_to_usecs(x));

But need to figure out what that "something" is. IIRC bspec
might not actually say which platforms have the "wait hblanks"
command. I gave it quick try on LNL but it didn't seem to work
there.

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2025-09-24 15:20 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-24 14:15 [PATCH 00/10] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 01/10] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 02/10] drm/i915/display: Add set_context_latency to crtc_state Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 03/10] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay() Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 04/10] drm/i915/vrr: Use SCL for computing guardband Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 05/10] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_delayed_vblank Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 06/10] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 07/10] drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX() Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 08/10] drm/i915/vrr: Clamp guardband as per hardware and timing constraints Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 09/10] drm/i915/display: Drop intel_vrr_vblank_delay and use set_context_latency Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 10/10] drm/i915/dsb: Inline dsb_vblank_delay() into intel_dsb_wait_for_delayed_vblank() Ankit Nautiyal
2025-09-24 15:20   ` Ville Syrjälä [this message]
2025-09-25  2:23   ` Ankit Nautiyal
2025-09-25  7:42     ` Ville Syrjälä
2025-09-24 14:37 ` ✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic (rev4) Patchwork
2025-09-24 14:52 ` ✗ CI.checksparse: warning " Patchwork
2025-09-24 15:13 ` ✓ Xe.CI.BAT: success " Patchwork
2025-09-24 17:13 ` ✓ i915.CI.BAT: " Patchwork
2025-09-24 19:21 ` ✓ Xe.CI.Full: " Patchwork
2025-09-25  0:20 ` ✗ i915.CI.Full: failure " Patchwork
2025-09-25  3:21 ` ✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic (rev5) Patchwork
2025-09-25  3:36 ` ✗ CI.checksparse: warning " Patchwork
2025-09-25  3:38 ` ✓ i915.CI.BAT: success " Patchwork
2025-09-25  3:55 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-25  9:16 ` ✗ i915.CI.Full: failure " Patchwork
2025-09-25 11:31 ` ✗ Xe.CI.Full: " Patchwork
2025-09-25 12:33 ` ✓ i915.CI.Full: success " Patchwork
2025-09-25 13:36 ` [PATCH 00/10] Introduce set_context_latency and refactor VRR/DSB timing logic Nautiyal, Ankit K

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