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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2025 00:11:21.6301 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa898674-a166-49fe-56e5-08ddffb5e2eb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9138 Received-SPF: permerror client-ip=2a01:111:f403:c112::7; envelope-from=nicolinc@nvidia.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Mon, Sep 29, 2025 at 02:36:22PM +0100, Shameer Kolothum wrote: > Accelerated SMMUv3 is only useful when the device can take advantage of > the host's SMMUv3 in nested mode. To keep things simple and correct, we > only allow this feature for vfio-pci endpoint devices that use the iommufd > backend. We also allow non-endpoint emulated devices like PCI bridges and > root ports, so that users can plug in these vfio-pci devices. We can only > enforce this if devices are cold plugged. For hotplug cases, give appropriate > warnings. > > Another reason for this limit is to avoid problems with IOTLB > invalidations. Some commands (e.g., CMD_TLBI_NH_ASID) lack an associated > SID, making it difficult to trace the originating device. If we allowed > emulated endpoint devices, QEMU would have to invalidate both its own > software IOTLB and the host's hardware IOTLB, which could slow things > down. > > Since vfio-pci devices in nested mode rely on the host SMMUv3's nested > translation (S1+S2), their get_address_space() callback must return the > system address space so that VFIO core can setup correct S2 mappings > for guest RAM. > > So in short: > - vfio-pci devices(with iommufd as backend) return the system address > space. > - bridges and root ports return the IOMMU address space. > > Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen With some nits: > + /* > + * We return the system address for vfio-pci devices(with iommufd as > + * backend) so that the VFIO core can set up Stage-2 (S2) mappings for > + * guest RAM. This is needed because, in the accelerated SMMUv3 case, > + * the host SMMUv3 runs in nested (S1 + S2) mode where the guest > + * manages its own S1 page tables while the host manages S2. > + * > + * We are using the global &address_space_memory here, as this will ensure > + * same system address space pointer for all devices behind the accelerated > + * SMMUv3s in a VM. That way VFIO/iommufd can reuse a single IOAS ID in > + * iommufd_cdev_attach(), allowing the Stage-2 page tables to be shared > + * within the VM instead of duplicating them for every SMMUv3 instance. > + */ > + if (vfio_pci) { > + return &address_space_memory; How about: /* * In the accelerated case, a vfio-pci device passed through via the iommufd * backend must stay in the system address space, as it is always translated * by its physical SMMU (using a stage-2-only STE or a nested STE), in which * case the stage-2 nesting parent page table is allocated by the vfio core, * backing up the system address space. * * So, return the system address space via the global address_space_memory. * The shared address_space_memory also allows devices under different vSMMU * instances in a VM to reuse a single nesting parent HWPT in the vfio core. */ ? And I think this would be clearer by having get_viommu_flags() in this patch. > diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c > index 1bcceddbc4..a8eb2d2426 100644 > --- a/hw/pci-bridge/pci_expander_bridge.c > +++ b/hw/pci-bridge/pci_expander_bridge.c > @@ -48,7 +48,6 @@ struct PXBBus { > char bus_path[8]; > }; > > -#define TYPE_PXB_PCIE_DEV "pxb-pcie" > OBJECT_DECLARE_SIMPLE_TYPE(PXBPCIEDev, PXB_PCIE_DEV) > > static GList *pxb_dev_list; > diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h > index a055fd8d32..b61360b900 100644 > --- a/include/hw/pci/pci_bridge.h > +++ b/include/hw/pci/pci_bridge.h > @@ -106,6 +106,7 @@ typedef struct PXBPCIEDev { > > #define TYPE_PXB_PCIE_BUS "pxb-pcie-bus" > #define TYPE_PXB_CXL_BUS "pxb-cxl-bus" > +#define TYPE_PXB_PCIE_DEV "pxb-pcie" > #define TYPE_PXB_DEV "pxb" > OBJECT_DECLARE_SIMPLE_TYPE(PXBDev, PXB_DEV) Maybe this can be a patch itself. Nicolin