Re: [PATCH] irqchip/gic-v5: Fix GIC CDEOI instruction encoding

[Catalin Marinas <catalin.marinas@arm.com>]

On Tue, Oct 07, 2025 at 10:58:12AM +0200, Lorenzo Pieralisi wrote:
> On Mon, Oct 06, 2025 at 04:24:18PM +0100, Catalin Marinas wrote:
> > On Mon, Oct 06, 2025 at 05:00:56PM +0200, Lorenzo Pieralisi wrote:
> > > My only remark there is that even as the code in mainline stands with
> > > GCC, it is not very clear that we rely on implicit XZR generation to
> > > make sure the instruction encoding generated is correct - it looks
> > > like a bit of a stretch to reuse a sysreg write with immediate value == 0
> > > to generate a system instruction write with Rt == 0b11111, it works
> > > but it is a bit opaque or at least not straighforward to grok.
> > > 
> > > Obviously the patch below improves LLVM code generation too in the process.
> > > 
> > > I don't know what's best - I admit I am on the fence on this one.
> > 
> > My concern is other cases where we may rely on this, so we might as well
> > go with a generic approach than fixing each case individually. If that's
> > the only case, I'll leave it to you and Marc do decide whichever you
> > prefer.
> 
> I will take your patch - added comments and rewrote the log for v2, with
> your Suggested-by (did not give you authorship let me know if that's OK
> please).

That's absolutely fine.

> One thing to mention, I added a Fixes: tag that goes back to the initial
> GICv5 commit, I don't know whether it is fixing more than that, it does
> not look like by a quick grep through kernel code but I am not sure.

This would do. If we find other problems, we'll backport it.

-- 
Catalin