From: Heikki Krogerus <heikki.krogerus@linux.intel.com>
To: Raag Jadav <raag.jadav@intel.com>
Cc: Andi Shyti <andi.shyti@kernel.org>,
lucas.demarchi@intel.com, rodrigo.vivi@intel.com,
intel-xe@lists.freedesktop.org, riana.tauro@intel.com
Subject: Re: [PATCH v1 2/2] drm/xe/i2c: Wire up reset/postinstall for I2C IRQ
Date: Wed, 8 Oct 2025 11:05:19 +0300 [thread overview]
Message-ID: <aOYbP6NCdKGtpcCj@kuha.fi.intel.com> (raw)
In-Reply-To: <aOYaSh5rlCElWurt@kuha.fi.intel.com>
On Wed, Oct 08, 2025 at 11:01:21AM +0300, Heikki Krogerus wrote:
> Hi,
>
> On Tue, Sep 30, 2025 at 01:22:33PM +0200, Raag Jadav wrote:
> > On Tue, Sep 30, 2025 at 01:13:57PM +0200, Andi Shyti wrote:
> > > Hi Raag,
> > >
> > > On Thu, Sep 25, 2025 at 01:38:35AM +0530, Raag Jadav wrote:
> > > > I2C IRQ needs to be routed to SGUnit or PUnit for the devices that support
> > > > it. Wire up reset/postinstall handles for I2C IRQ to take care of this.
> > > >
> > > > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > >
> > > Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
> >
> > Awesome, thanks Andi.
> >
> > Heikki, I can integrate your DISABLE_MSI changes which I'm assuming
> > will be in the same path here?
>
> Yes, that would be awesome!
So something like this squashed into this patch?
diff --git a/drivers/gpu/drm/xe/regs/xe_i2c_regs.h b/drivers/gpu/drm/xe/regs/xe_i2c_regs.h
index f2e455e2bfe4..396d78c3b6a3 100644
--- a/drivers/gpu/drm/xe/regs/xe_i2c_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_i2c_regs.h
@@ -16,6 +16,7 @@
#define I2C_BRIDGE_PCICFGCTL XE_REG(I2C_BRIDGE_OFFSET + 0x200)
#define ACPI_INTR_EN REG_BIT(1)
+#define DISABLE_MSI_CAP REG_BIT(29)
#define I2C_CONFIG_CMD XE_REG(I2C_CONFIG_SPACE_OFFSET + PCI_COMMAND)
#define I2C_CONFIG_PMCSR XE_REG(I2C_CONFIG_SPACE_OFFSET + 0x84)
diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c
index 69f39df5a692..8a4ba6a411e4 100644
--- a/drivers/gpu/drm/xe/xe_i2c.c
+++ b/drivers/gpu/drm/xe/xe_i2c.c
@@ -189,7 +189,7 @@ void xe_i2c_irq_reset(struct xe_device *xe)
if (!xe_i2c_irq_present(xe))
return;
- xe_mmio_rmw32(mmio, I2C_BRIDGE_PCICFGCTL, ACPI_INTR_EN, 0);
+ xe_mmio_rmw32(mmio, I2C_BRIDGE_PCICFGCTL, ACPI_INTR_EN, DISABLE_MSI_CAP);
}
void xe_i2c_irq_postinstall(struct xe_device *xe)
@@ -199,7 +199,7 @@ void xe_i2c_irq_postinstall(struct xe_device *xe)
if (!xe_i2c_irq_present(xe))
return;
- xe_mmio_rmw32(mmio, I2C_BRIDGE_PCICFGCTL, 0, ACPI_INTR_EN);
+ xe_mmio_rmw32(mmio, I2C_BRIDGE_PCICFGCTL, DISABLE_MSI_CAP, ACPI_INTR_EN);
}
static int xe_i2c_irq_map(struct irq_domain *h, unsigned int virq,
--
heikki
next prev parent reply other threads:[~2025-10-08 8:05 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-24 20:08 [PATCH v1 0/2] Wire up reset/postinstall for I2C IRQ Raag Jadav
2025-09-24 20:08 ` [PATCH v1 1/2] drm/xe/i2c: Introduce xe_i2c_irq_present() Raag Jadav
2025-09-30 11:08 ` Andi Shyti
2025-10-08 8:08 ` Heikki Krogerus
2025-09-24 20:08 ` [PATCH v1 2/2] drm/xe/i2c: Wire up reset/postinstall for I2C IRQ Raag Jadav
2025-09-30 11:13 ` Andi Shyti
2025-09-30 11:22 ` Raag Jadav
2025-10-08 8:01 ` Heikki Krogerus
2025-10-08 8:05 ` Heikki Krogerus [this message]
2025-10-09 6:14 ` Raag Jadav
2025-10-09 6:12 ` Raag Jadav
2025-10-08 8:09 ` Heikki Krogerus
2025-09-24 20:16 ` ✓ CI.KUnit: success for " Patchwork
2025-09-24 21:13 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-25 3:42 ` ✗ Xe.CI.Full: failure " Patchwork
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