From: Yao Zi <ziyao@disroot.org>
To: Uros Stajic <uros.stajic@htecgroup.com>,
"u-boot@lists.denx.de" <u-boot@lists.denx.de>
Cc: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,
Chao-ying Fu <cfu@mips.com>
Subject: Re: [PATCH v4 10/10] cmd: riscv: Add 'startharts' command to start multiple harts
Date: Thu, 9 Oct 2025 11:43:55 +0000 [thread overview]
Message-ID: <aOef-6YZKbyk9RsD@pie> (raw)
In-Reply-To: <20250819103021.1518687-11-uros.stajic@htecgroup.com>
On Tue, Aug 19, 2025 at 10:34:39AM +0000, Uros Stajic wrote:
> From: Chao-ying Fu <cfu@mips.com>
>
> Introduce the 'startharts' command for RISC-V targets, which prints
> or executes commands to power up and reset all harts and jump to
> 0x80000000. The command supports optional cluster/core count and
> immediate execution via the 'g' argument.
>
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Uros Stajic <uros.stajic@htecgroup.com>
I noticed in OpenSBI, P8700 already implements HSM extension[1], which
means it's usually unnecessary to take care of SMP stuff in U-Boot. Do
you still want the new startharts command?
In summary, there are two possible solutions to support SMP for RISC-V
systems with U-Boot and OpenSBI with minimal effort, where SPL runs in M
mode and proper U-Boot runs in S mode,
1. Release all the HARTs in SPL stage. With SMP enabled in U-Boot SPL, a
core is randomly picked to run the main part of U-Boot SPL, and the
others simply spin and wait.
When all the initialization and load are finished, an IPI message is
sent to each spinning HART, releasing them to the next-level
firmware's entry (OpenSBI here), see smp_call_function called in
spl_opensbi.c.
This is usually more appropriate when your platform releases all
HARTs when powered up, in which case you could omit the code of
releasing all HARTs to U-Boot SPL. This requires a proper
implementation of IPI, and proper description of all HARTs in
devicetree.
2. Implement SMP bring-up code totally in OpenSBI. U-Boot itself is
expected to run in single thread, so it's unnecessary to bring up any
cores in U-Boot.
RISC-V SBI defines a HART-State-Management extension (HSM). You could
implement HART bring-up code in OpenSBI, and expecting kernel (maybe
Linux) brings up the rest HARTs through the extension.
Looking through the startharts command, P8700 does require manual steps
to release non-boot cores, which makes option 1 less appropriate since
it introduces more platform-specific code to U-Boot, while it has been
already implemented in OpenSBI, becoming some duplicated code.
I suggest moving to HSM extension entirely and avoiding introducing any
SMP code in U-Boot for your port. Or, if you still prefer to implement
it in U-Boot, please re-use the existing framework of bring up HARTs
(smp_call_function, proper IPI, etc.). This could definitely helps
code review and future maintenance.
Best regards,
Yao Zi
[1]: https://github.com/riscv-software-src/opensbi/commit/66ab965e54017292d530033ffaae127389c45458
next prev parent reply other threads:[~2025-10-09 11:44 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-19 10:31 [PATCH v4 00/10] riscv: Add support for P8700 platform on Boston board Uros Stajic
2025-08-19 10:31 ` [PATCH v4 01/10] riscv: Add initial support for P8700 SoC Uros Stajic
2025-10-09 10:23 ` Yao Zi
2026-01-13 7:12 ` Uros Stajic
2025-08-19 10:32 ` [PATCH v4 02/10] board: boston-riscv: Add initial support for P8700 Boston board Uros Stajic
2025-10-09 10:46 ` Yao Zi
2025-08-19 10:32 ` [PATCH v4 03/10] gpio: Add GPIO driver for Intel EG20T Uros Stajic
2025-08-19 10:32 ` [PATCH v4 04/10] pci: xilinx: Avoid writing memory base/limit for root bridge Uros Stajic
2025-08-19 10:32 ` [PATCH v4 05/10] riscv: Add support for MIPS GIC syscon on RISC-V SoCs Uros Stajic
2025-10-09 10:53 ` Yao Zi
2025-08-19 10:33 ` [PATCH v4 06/10] net: pch_gbe: Add PHY reset and MAC address fallback for RISC-V Uros Stajic
2025-08-19 10:33 ` [PATCH v4 07/10] libfdt: Allow non-64b aligned memreserve entries Uros Stajic
2025-08-19 10:33 ` [PATCH v4 08/10] riscv: p8700: Add Coherence Manager (CM) and IOCU support Uros Stajic
2025-08-19 10:34 ` [PATCH v4 09/10] riscv: boston: Add support for LED character display command Uros Stajic
2025-10-09 11:15 ` Yao Zi
2026-01-13 8:19 ` Uros Stajic
2025-08-19 10:34 ` [PATCH v4 10/10] cmd: riscv: Add 'startharts' command to start multiple harts Uros Stajic
2025-10-09 11:43 ` Yao Zi [this message]
2026-01-13 8:20 ` Uros Stajic
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aOef-6YZKbyk9RsD@pie \
--to=ziyao@disroot.org \
--cc=Djordje.Todorovic@htecgroup.com \
--cc=cfu@mips.com \
--cc=u-boot@lists.denx.de \
--cc=uros.stajic@htecgroup.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.