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[34.76.240.140]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4711444d919sm77014225e9.14.2025.10.17.04.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 04:04:27 -0700 (PDT) Date: Fri, 17 Oct 2025 11:04:24 +0000 From: Mostafa Saleh To: Jacob Pan Cc: linux-kernel@vger.kernel.org, "iommu@lists.linux.dev" , Will Deacon , Jason Gunthorpe , Robin Murphy , Nicolin Chen , Zhang Yu , Jean Philippe-Brucker , Alexander Grest Subject: Re: [PATCH 2/2] iommu/arm-smmu-v3: Improve CMDQ lock fairness and efficiency Message-ID: References: <20250924175438.7450-1-jacob.pan@linux.microsoft.com> <20250924175438.7450-3-jacob.pan@linux.microsoft.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250924175438.7450-3-jacob.pan@linux.microsoft.com> On Wed, Sep 24, 2025 at 10:54:38AM -0700, Jacob Pan wrote: > From: Alexander Grest > > The SMMU CMDQ lock is highly contentious when there are multiple CPUs > issuing commands on an architecture with small queue sizes e.g 256 > entries. > > The lock has the following states: > - 0: Unlocked > - >0: Shared lock held with count > - INT_MIN+N: Exclusive lock held, where N is the # of shared waiters > - INT_MIN: Exclusive lock held, no shared waiters > > When multiple CPUs are polling for space in the queue, they attempt to > grab the exclusive lock to update the cons pointer from the hardware. If > they fail to get the lock, they will spin until either the cons pointer > is updated by another CPU. > > The current code allows the possibility of shared lock starvation > if there is a constant stream of CPUs trying to grab the exclusive lock. > This leads to severe latency issues and soft lockups. > > To mitigate this, we release the exclusive lock by only clearing the sign > bit while retaining the shared lock waiter count as a way to avoid > starving the shared lock waiters. > > Also deleted cmpxchg loop while trying to acquire the shared lock as it > is not needed. The waiters can see the positive lock count and proceed > immediately after the exclusive lock is released. > > Exclusive lock is not starved in that submitters will try exclusive lock > first when new spaces become available. > > In a staged test where 32 CPUs issue SVA invalidations simultaneously on > a system with a 256 entry queue, the madvise (MADV_DONTNEED) latency > dropped by 50% with this patch and without soft lockups. > > Signed-off-by: Alexander Grest > Signed-off-by: Jacob Pan > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 24 ++++++++++++--------- > 1 file changed, 14 insertions(+), 10 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 9b63525c13bb..9b7c01b731df 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -481,20 +481,19 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) > */ > static void arm_smmu_cmdq_shared_lock(struct arm_smmu_cmdq *cmdq) > { > - int val; > - > /* > - * We can try to avoid the cmpxchg() loop by simply incrementing the > - * lock counter. When held in exclusive state, the lock counter is set > - * to INT_MIN so these increments won't hurt as the value will remain > - * negative. > + * We can simply increment the lock counter. When held in exclusive > + * state, the lock counter is set to INT_MIN so these increments won't > + * hurt as the value will remain negative. This will also signal the > + * exclusive locker that there are shared waiters. Once the exclusive > + * locker releases the lock, the sign bit will be cleared and our > + * increment will make the lock counter positive, allowing us to > + * proceed. > */ > if (atomic_fetch_inc_relaxed(&cmdq->lock) >= 0) > return; > > - do { > - val = atomic_cond_read_relaxed(&cmdq->lock, VAL >= 0); > - } while (atomic_cmpxchg_relaxed(&cmdq->lock, val, val + 1) != val); > + atomic_cond_read_relaxed(&cmdq->lock, VAL >= 0); I think that should be "VAL > 0", as it is guaranteed that we hold the shared lock at this point. Otherwise, Reviewed-by: Mostafa Saleh Thanks, Mostafa > } > > static void arm_smmu_cmdq_shared_unlock(struct arm_smmu_cmdq *cmdq) > @@ -521,9 +520,14 @@ static bool arm_smmu_cmdq_shared_tryunlock(struct arm_smmu_cmdq *cmdq) > __ret; \ > }) > > +/* > + * Only clear the sign bit when releasing the exclusive lock this will > + * allow any shared_lock() waiters to proceed without the possibility > + * of entering the exclusive lock in a tight loop. > + */ > #define arm_smmu_cmdq_exclusive_unlock_irqrestore(cmdq, flags) \ > ({ \ > - atomic_set_release(&cmdq->lock, 0); \ > + atomic_fetch_and_release(~INT_MIN, &cmdq->lock); \ > local_irq_restore(flags); \ > }) > > -- > 2.43.0 >