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From: Zhao Liu <zhao1.liu@intel.com>
To: Ewan Hai <ewanhai-oc@zhaoxin.com>
Cc: pbonzini@redhat.com, qemu-devel@nongnu.org
Subject: Re: [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server CPU model
Date: Fri, 24 Oct 2025 15:15:55 +0800	[thread overview]
Message-ID: <aPsnqxDZR4KxgcdN@intel.com> (raw)
In-Reply-To: <20250923021133.190725-4-ewanhai-oc@zhaoxin.com>

On Mon, Sep 22, 2025 at 10:11:33PM -0400, Ewan Hai wrote:
> Date: Mon, 22 Sep 2025 22:11:33 -0400
> From: Ewan Hai <ewanhai-oc@zhaoxin.com>
> Subject: [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server CPU
>  model
> X-Mailer: git-send-email 2.34.1
> 
> Shijidadao-Server hardware enables IA32_CORE_CAPABILITIES and relies on
> the SPLIT_LOCK_DETECT feature. When the kernel has not yet virtualized
> this MSR, KVM filters the capability and QEMU emits a warning.
> 
> This patch retains the core-capability bit in the CPU model so it will
> take effect once KVM support becomes available.
> 
> In QEMU, vCPU models default to '.version = 1'. Since there is currently
> no '.features[index]' mapping for the "x-force-cpuid-0x1f" property, this
> patch adds that property to the v1 version of the model.

I'm preparing the CPU model for Diamond Rapids, and also meet this
issue.

Well, I happen to have a patch for this and I think you could give it
a try. :)

Thanks,
Zhao



  reply	other threads:[~2025-10-24  6:54 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-23  2:11 [PATCH 0/3] target/i386: Add support for Zhaoxin Shijidadao vCPU models Ewan Hai
2025-09-23  2:11 ` [PATCH 1/3] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs Ewan Hai
2025-09-23  2:11 ` [PATCH 2/3] target/i386: Introduce Zhaoxin Shijidadao-Client CPU model Ewan Hai
2025-09-23  2:11 ` [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server " Ewan Hai
2025-10-24  7:15   ` Zhao Liu [this message]
2025-10-27  3:42     ` Ewan Hai
2025-10-27  6:14       ` Zhao Liu
2025-10-24  7:18   ` [PATCH] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f Zhao Liu

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