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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nPyiuHMe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5C74EC4CEF8; Fri, 7 Nov 2025 17:44:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762537459; bh=vUXVxSlqnlNC2tbqdDtNDX2ebfN1pxrOSHo7fEAw12Y=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=nPyiuHMehYfo3g71SbYqe2NgLFsFFVMXj4vT7odT8obZ75hR69ps6sjFs7W80FROW hsZ6pFPi88FRX2UD5Cm6+HC771R2+6brdPgwss1tTPliJYG2gsSBF458IPzk2biX4F RNucbaE7viPNG0fA44kswLaF1vDw1xdcVm24mb9XAzFuUudPzZP2zjF7PkN8uRFPi3 v/mOgSdMqYEV8CsIQEdTu+nRG2wJjym0S+q1IPuIpdL1evYiCtDNkU1SRaMYdZVVx9 XorcU2JIf9Jvp9EVNM6QQghP36vq0hw9+ssncfOeRNtG4AI3En7iA7OjYAWpfAG3M0 mh5MCTsRK1scA== Date: Fri, 7 Nov 2025 09:44:17 -0800 From: Drew Fustini To: Radim =?utf-8?B?S3LEjW3DocWZ?= Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kornel =?utf-8?Q?Dul=C4=99ba?= , Adrien Ricciardi , James Morse , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , Conor Dooley , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv Subject: Re: [PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext Message-ID: References: <20251007-ssqosid-v4-0-e8b57e59d812@kernel.org> <20251007-ssqosid-v4-3-e8b57e59d812@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Mon, Oct 13, 2025 at 11:06:50AM +0200, Radim Krčmář wrote: > 2025-10-11T11:35:46-07:00, Drew Fustini : > > On Thu, Oct 09, 2025 at 08:47:27AM +0200, Radim Krčmář wrote: > >> 2025-10-07T23:21:12-07:00, Drew Fustini : > >> > diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h > >> > +static inline void __switch_to_srmcfg(struct task_struct *next) > >> > +{ > >> > + u32 *cpu_srmcfg_ptr = this_cpu_ptr(&cpu_srmcfg); > >> > + u32 thread_srmcfg; > >> > + > >> > + thread_srmcfg = READ_ONCE(next->thread.srmcfg); > >> > + > >> > + if (thread_srmcfg != *cpu_srmcfg_ptr) { > >> > >> Wouldn't prev->thread.srmcfg have the value of CSR_SRMCFG when executing > >> switch_to? > > > > Thanks for reviewing. Yes, you are right that prev->thread.srmcfg should > > have same value as CSR_SRMCFG. Are you suggesting that the cpu_srmcfg is > > not necessary as prev->thread.srmcfg should have same value? > > Yes, it would be more consistent with other context switched state. > I just wasn't sure if srmcfg doesn't have special race conditions. I did some testing and the per-cpu cache of CSR_SRMCFG is needed. This is because thread.srmcfg is changed asynchronously from when CSR_SRMCFG is updated in __switch_to_srmcfg. The srmcfg value for a thread is updated when a user writes the pid to a control group's tasks file in the resctrl virtual filesystem: void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32 rmid) { u32 srmcfg; WARN_ON_ONCE((closid & SRMCFG_RCID_MASK) != closid); WARN_ON_ONCE((rmid & SRMCFG_MCID_MASK) != rmid); srmcfg = rmid << SRMCFG_MCID_SHIFT; srmcfg |= closid; WRITE_ONCE(tsk->thread.srmcfg, srmcfg); } I'm getting a full patch series ready that has both the Ssqosid and the CBQRI resctrl patches, and I will post that soon. I'm also preparing a freshly rebased Qemu series that adds the CBQRI controllers. Thanks, Drew