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[35.185.200.132]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7b0c953d103sm4148113b3a.5.2025.11.07.16.28.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 16:28:09 -0800 (PST) Date: Sat, 8 Nov 2025 00:28:04 +0000 From: David Matlack To: Jason Gunthorpe Cc: David Woodhouse , iommu@lists.linux.dev, Joerg Roedel , Robin Murphy , Will Deacon , Lu Baolu , Kevin Tian , patches@lists.linux.dev, Tina Zhang , Wei Wang Subject: Re: [PATCH v3 00/10] Convert Intel VT-d to use the generic iommu page table Message-ID: References: <0-v3-634ccd3efce0+16d38-iommu_pt_vtd_jgg@nvidia.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0-v3-634ccd3efce0+16d38-iommu_pt_vtd_jgg@nvidia.com> On 2025-10-23 03:22 PM, Jason Gunthorpe wrote: > Replace the VT-d iommu_domain implementation of the VT-d second stage and > first stage page tables with the iommupt VTDSS and x86_64 > pagetables. x86_64 is shared with the AMD driver. > > VT-d has HW that requires an incoherent page table walker, the majority of > the patches are adding generic support for the required cache flushing to > iommupt. This is modeled after the existing ARM64 version and is intended > to be re-used there. > > Applies on top of the AMD conversion: > https://patch.msgid.link/r/0-v2-5c26bde5c22d+58b-iommu_pt_jgg@nvidia.com > > This is on github: https://github.com/jgunthorpe/linux/commits/iommu_pt_vtd I ran VFIO selftests against this series and did not detect any regressions. Notably, vfio_dma_mapping_test confirmed that this series did not regress VFIO's or IOMMUFD's ability to map 2MB and 1GB HugeTLB pages as 2MB and 1GB entries in the I/O page tables as expected. And vfio_pci_driver_test validates that a device (Intel DSA in this case) can do DMA, and exercises I/O faulting handling. Tested-by: David Matlack