Re: [PATCH net-next v5 05/15] octeontx2-af: Add support for CPT second pass

[Simon Horman <horms@kernel.org>]

On Sun, Oct 26, 2025 at 08:39:00PM +0530, Tanmay Jagdale wrote:
> From: Rakesh Kudurumalla <rkudurumalla@marvell.com>
> 
> Implemented mailbox to add mechanism to allocate a
> rq_mask and apply to nixlf to toggle RQ context fields
> for CPT second pass packets.
> 
> Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
> Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>

...

> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> index c3d6f363bf61..95f93a29a00e 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> @@ -6632,3 +6632,128 @@ void rvu_block_bcast_xon(struct rvu *rvu, int blkaddr)
>  	cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(0));
>  	rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(0), cfg);
>  }
> +
> +static inline void
> +configure_rq_mask(struct rvu *rvu, int blkaddr, int nixlf,
> +		  u8 rq_mask, bool enable)

Hi Rakesh and Tanmay,

Please don't use inline in C files unless there is a demonstrable - usually
performance - reason to do so.  Rather, please let the compiler inline code
as it sees fit.

> +{
> +	u64 cfg, reg;
> +
> +	cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(nixlf));
> +	reg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_CFG(nixlf));
> +	if (enable) {
> +		cfg |= NIX_AF_LFX_RX_IPSEC_CFG1_RQ_MASK_ENA;
> +		reg &= ~NIX_AF_LFX_CFG_RQ_CPT_MASK_SEL;
> +		reg |= FIELD_PREP(NIX_AF_LFX_CFG_RQ_CPT_MASK_SEL, rq_mask);
> +	} else {
> +		cfg &= ~NIX_AF_LFX_RX_IPSEC_CFG1_RQ_MASK_ENA;
> +		reg &= ~NIX_AF_LFX_CFG_RQ_CPT_MASK_SEL;
> +	}
> +	rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(nixlf), cfg);
> +	rvu_write64(rvu, blkaddr, NIX_AF_LFX_CFG(nixlf), reg);
> +}
> +
> +static inline void
> +configure_spb_cpt(struct rvu *rvu, int blkaddr, int nixlf,
> +		  struct nix_rq_cpt_field_mask_cfg_req *req, bool enable)

Here too.

> +{
> +	u64 cfg;
> +
> +	cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(nixlf));
> +
> +	/* Clear the SPB bit fields */
> +	cfg &= ~NIX_AF_LFX_RX_IPSEC_CFG1_SPB_CPT_ENA;
> +	cfg &= ~NIX_AF_LFX_RX_IPSEC_CFG1_SPB_CPT_SZM1;
> +	cfg &= ~NIX_AF_LFX_RX_IPSEC_CFG1_SPB_AURA;
> +
> +	if (enable) {
> +		cfg |= NIX_AF_LFX_RX_IPSEC_CFG1_SPB_CPT_ENA;
> +		cfg |= FIELD_PREP(NIX_AF_LFX_RX_IPSEC_CFG1_SPB_CPT_SZM1,
> +				  req->ipsec_cfg1.spb_cpt_sizem1);
> +		cfg |= FIELD_PREP(NIX_AF_LFX_RX_IPSEC_CFG1_SPB_AURA,
> +				  req->ipsec_cfg1.spb_cpt_aura);
> +	}
> +
> +	rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(nixlf), cfg);
> +}

...