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Tue, 28 Oct 2025 21:26:51 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 28 Oct 2025 21:26:51 -0700 Received: from Asurada-Nvidia (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Tue, 28 Oct 2025 21:26:50 -0700 Date: Tue, 28 Oct 2025 21:26:49 -0700 From: Nicolin Chen To: Shameer Kolothum CC: "eric.auger@redhat.com" , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , Jason Gunthorpe , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "yi.l.liu@intel.com" , "shameerkolothum@gmail.com" Subject: Re: [PATCH v4 19/27] hw/arm/smmuv3-accel: Install S1 bypass hwpt on reset Message-ID: References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-20-skolothumtho@nvidia.com> <76ce5b05-98fe-4682-a5ca-2f87b7535f35@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 04:27:08.0111 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e82ab1c7-3482-4880-ce9d-08de16a36c13 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6584 Received-SPF: permerror client-ip=2a01:111:f403:c112::5; envelope-from=nicolinc@nvidia.com; helo=CY7PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Mon, Oct 27, 2025 at 07:51:15AM -0700, Shameer Kolothum wrote: > > On 10/17/25 1:19 AM, Nicolin Chen wrote: > > > On Mon, Sep 29, 2025 at 02:36:35PM +0100, Shameer Kolothum wrote: > > >> When the guest reboots with devices in nested mode (S1 + S2), any > > QEMU/UEFI > > >> access to those devices can fail because S1 translation is not valid during > > >> the reboot. For example, a passthrough NVMe device may hold GRUB boot > > info > > >> that UEFI tries to read during the reboot. > > >> > > >> Set S1 to bypass mode during reset to avoid such failures. > > > GBPA is set to bypass on reset so I think it's fine. Yet, maybe the > > > code should check that. > > > > shouldn't we check its actual value before setting bypass? > > > > By the way the spec says is ABORT is set to 0x0: > > "Do not abort incoming transactions. Transactions bypass the SMMU with > > attributes given by other fields in this register." > > > > Wondering about those attributes and they can apply on the host? > > That’s right. There are other attributes there. Currently kernel only > support, > > * @ste: The first two double words of the user space Stream Table Entry for > * the translation. Must be little-endian. > * Allowed fields: (Refer to "5.2 Stream Table Entry" in SMMUv3 HW Spec) > * - word-0: V, Cfg, S1Fmt, S1ContextPtr, S1CDMax > * - word-1: EATS, S1DSS, S1CIR, S1COR, S1CSH, S1STALLD > > If other attributes make sense, we may have to update kernel. I will add a note > here, so that we can update it if required. I think Nicolin is looking into this. According to SMMU spec 6.3 GBPA register's Additional information: - If SMMU_IDR1.ATTR_TYPES_OVR == 0, MTCFG, SHCFG, ALLOCCFG are effectively fixed as Use incoming and it is IMPLEMENTATION SPECIFIC whether these fields read as zero or a previously written value. In this case, MemAttr reads as UNKNOWN. - If SMMU_IDR1.ATTR_PERMS_OVR == 0, INSTCFG and PRIVCFG are effectively fixed as Use incoming and it is IMPLEMENTATION SPECIFIC whether these fields read as zero or a previously written value. On the other hand, QEMU seems to set both OVR fields to 0, so all those "other attributes" wouldn't be necessarily forwarded to the kernel? Nicolin