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Thu, 30 Oct 2025 00:35:47 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 30 Oct 2025 00:35:46 -0700 Received: from Asurada-Nvidia (10.127.8.13) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Thu, 30 Oct 2025 00:35:45 -0700 Date: Thu, 30 Oct 2025 00:35:43 -0700 From: Nicolin Chen To: Shameer Kolothum CC: "eric.auger@redhat.com" , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , Jason Gunthorpe , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "yi.l.liu@intel.com" , "shameerkolothum@gmail.com" Subject: Re: [PATCH v4 19/27] hw/arm/smmuv3-accel: Install S1 bypass hwpt on reset Message-ID: References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-20-skolothumtho@nvidia.com> <76ce5b05-98fe-4682-a5ca-2f87b7535f35@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(7416014)(36860700013)(1800799024)(13003099007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2025 07:36:01.1323 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82211c0b-a959-4a2d-703d-08de1786f9a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECDA.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9219 Received-SPF: permerror client-ip=2a01:111:f403:c111::5; envelope-from=nicolinc@nvidia.com; helo=DM1PR04CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Wed, Oct 29, 2025 at 10:28:35PM -0700, Nicolin Chen wrote: > On Wed, Oct 29, 2025 at 11:19:59AM -0700, Shameer Kolothum wrote: > > > According to SMMU spec 6.3 GBPA register's Additional information: > > > - If SMMU_IDR1.ATTR_TYPES_OVR == 0, MTCFG, SHCFG, ALLOCCFG are > > > effectively fixed as Use incoming and it is IMPLEMENTATION > > > SPECIFIC whether these fields read as zero or a previously > > > written value. In this case, MemAttr reads as UNKNOWN. > > > - If SMMU_IDR1.ATTR_PERMS_OVR == 0, INSTCFG and PRIVCFG are > > > effectively fixed as Use incoming and it is IMPLEMENTATION > > > SPECIFIC whether these fields read as zero or a previously > > > written value. > > > > > > On the other hand, QEMU seems to set both OVR fields to 0, so all > > > those "other attributes" wouldn't be necessarily forwarded to the > > > kernel? > > > > OK. Based on the QEMU OVR value, GBPA now resets to 0x1000, meaning > > SHCFG = 0b01 (Use incoming). However, in the current vSTE bypass/abort > > cases, SHCFG is set to 0b00 (Non-shareable). > > Ah, no, my bad. SHCFG will need to be forwarded, if the hw_info > call reports that host SMMU has SMMU_IDR1.ATTR_TYPES_OVR == 1. > > So, the SHCFG=incoming has been the default case, but to support > a non-incoming configuration, kernel needs to allow SHCFG in the > vSTE. > > > However, I think the SHCFG will be overridden by S2FWB. > > I don't think S2FWB affects SHCFG. SHCFG has been set by kernel: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c?h=v6.18-rc3#n1681 Hmm, the table "13.5 Summary of attribute/permission configuration fields" in SMMU spec doesn't seem to show the complete picture.. I found the pseudo code in ARMv8 spec telling the details: shared/translation/attrs/S2AttrDecode // S2AttrDecode() // ============== // Converts the Stage 2 attribute fields into orthogonal attributes and hints MemoryAttributes S2AttrDecode(bits(2) SH, bits(4) attr, AccType acctype) MemoryAttributes memattrs; apply_force_writeback = HaveStage2MemAttrControl() && HCR_EL2.FWB == '1'; // Device memory if (apply_force_writeback && attr<2> == '0') || attr<3:2> == '00' then memattrs.memtype = MemType_Device; case attr<1:0> of when '00' memattrs.device = DeviceType_nGnRnE; when '01' memattrs.device = DeviceType_nGnRE; when '10' memattrs.device = DeviceType_nGRE; when '11' memattrs.device = DeviceType_GRE; // Normal memory elsif apply_force_writeback then if attr<2> == '1' then memattrs.memtype = MemType_Normal; memattrs.inner.attrs = attr<1:0>; memattrs.outer.attrs = attr<1:0>; memattrs.shareable = SH<1> == '1'; memattrs.outershareable = SH == '10'; elsif attr<1:0> != '00' then memattrs.memtype = MemType_Normal; memattrs.outer = S2ConvertAttrsHints(attr<3:2>, acctype); memattrs.inner = S2ConvertAttrsHints(attr<1:0>, acctype); memattrs.shareable = SH<1> == '1'; memattrs.outershareable = SH == '10'; else memattrs = MemoryAttributes UNKNOWN; // Reserved return MemAttrDefaults(memattrs); So, it seems that you are right. SHCFG will be overridden by S2FWB. However, we have CPU like Grace that doesn't have S2FWB.. Nicolin