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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2025 22:02:23.6379 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bab19fda-d6bf-4180-4ccb-08de18c92bf9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF2FA070BDF Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=nicolinc@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Fri, Oct 31, 2025 at 10:49:45AM +0000, Shameer Kolothum wrote: > +static bool > +smmuv3_accel_dev_alloc_viommu(SMMUv3AccelDevice *accel_dev, > + HostIOMMUDeviceIOMMUFD *idev, Error **errp) Let's make it simply do alloc() on s_accel: static bool smmuv3_accel_alloc_viommu(SMMUv3AccelState *s_accel, HostIOMMUDeviceIOMMUFD *idev, Error **errp) Then.. > + SMMUDevice *sdev = &accel_dev->sdev; > + SMMUState *bs = sdev->smmu; > + SMMUv3State *s = ARM_SMMUV3(bs); > + SMMUv3AccelState *s_accel = s->s_accel; Drop these. > + if (s_accel->vsmmu) { > + accel_dev->vsmmu = s_accel->vsmmu; > + return true; > + } And this. > +static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int devfn, > + HostIOMMUDevice *hiod, Error **errp) [...] > + if (!smmuv3_accel_dev_alloc_viommu(accel_dev, idev, errp)) { > + error_append_hint(errp, "Device 0x%x: Unable to alloc viommu", sid); > + return false; > + } And here: if (!s_accel->vsmmu && !smmuv3_accel_alloc_viommu(s_accel, idev, errp)) { error_append_hint(errp, "Device 0x%x: Unable to alloc viommu", sid); return false; } accel_dev->idev = idev; accel_dev->vsmmu = s_accel->vsmmu; Feels slightly cleaner. > +/* > + * Represents a virtual SMMU instance backed by an iommufd vIOMMU object. > + * Holds references to the core iommufd vIOMMU object and to proxy HWPTs I read "reference" as a pointer, yet... > + * (bypass and abort) used for device attachment. > + */ > +typedef struct SMMUViommu { > + IOMMUFDBackend *iommufd; > + IOMMUFDViommu viommu; > + uint32_t bypass_hwpt_id; > + uint32_t abort_hwpt_id; ...viommu is a containment and two HWPTs are IDs. So, it'd sound more accurate, being: /* * Represents a virtual SMMU instance backed by an iommufd vIOMMU object. * Holds bypass and abort proxy HWPT ids used for device attachment. */ > +typedef struct SMMUv3AccelState { > + SMMUViommu *vsmmu; > +} SMMUv3AccelState; Hmm, maybe we don't need another layer of structure. Every access or validation to s_accel is for s_accel->vsmmu. e.g. if (!s_accel || !s_accel->vsmmu) { could be if (!s_accel) { So, let's try merging them into one. And feel free to leave one of your favorite. Nic