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Tue, 4 Nov 2025 10:44:31 -0800 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Nov 2025 10:44:30 -0800 Received: from Asurada-Nvidia (10.127.8.11) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Tue, 4 Nov 2025 10:44:29 -0800 Date: Tue, 4 Nov 2025 10:44:27 -0800 From: Nicolin Chen To: Jason Gunthorpe CC: Shameer Kolothum , Eric Auger , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "yi.l.liu@intel.com" , Krishnakant Jaju Subject: Re: [PATCH v5 15/32] hw/pci/pci: Introduce optional get_msi_address_space() callback Message-ID: References: <20251104145157.GF1537560@nvidia.com> <20251104151234.GG1537560@nvidia.com> <20251104153535.GH1537560@nvidia.com> <20251104174152.GI1537560@nvidia.com> <20251104180928.GK1537560@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(7416014)(376014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 18:44:47.3158 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddbf0f82-cd64-47d5-7319-08de1bd23a99 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE16.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7912 Received-SPF: permerror client-ip=2a01:111:f403:c007::2; envelope-from=nicolinc@nvidia.com; helo=MW6PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.788, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Tue, Nov 04, 2025 at 02:09:28PM -0400, Jason Gunthorpe wrote: > On Tue, Nov 04, 2025 at 09:57:53AM -0800, Nicolin Chen wrote: > > On Tue, Nov 04, 2025 at 01:41:52PM -0400, Jason Gunthorpe wrote: > > > On Tue, Nov 04, 2025 at 09:11:55AM -0800, Nicolin Chen wrote: > > > > On Tue, Nov 04, 2025 at 11:35:35AM -0400, Jason Gunthorpe wrote: > > > > > On Tue, Nov 04, 2025 at 03:20:59PM +0000, Shameer Kolothum wrote: > > > > > > > On Tue, Nov 04, 2025 at 02:58:44PM +0000, Shameer Kolothum wrote: > > > > > > > > > Sure it is trapped, but nothing should be looking at the MSI address > > > > > > > > > from the guest, it is meaningless and wrong information. Just ignore > > > > > > > > > it. > > > > > > > > > > > > > > > > Hmm.. we need to setup the doorbell address correctly. > > > > > > > > > > > > > > > If we don't do the translation here, it will use the Guest IOVA > > > > > > > > address. Remember, we are using the IORT RMR identity mapping to get > > > > > > > > MSI working. > > > > > > > > > > > > > > Either you use the RMR value, which is forced by the kernel into the > > > > > > > physical MSI through iommufd and kernel ignores anything qemu > > > > > > > does. So fully ignore the guest's vMSI address. > > > > > > > > > > > > Well, we are sort of trying to do the same through this patch here. > > > > > > But to avoid a "translation" completely it will involve some changes to > > > > > > Qemu pci subsystem. I think this is the least intrusive path I can think > > > > > > of now. And this is a one time setup mostly. > > > > > > > > > > Should be explained in the commit message that the translation is > > > > > pointless. I'm not sure about this, any translation seems risky > > > > > because it could fail. The guest can use any IOVA for MSI and none may > > > > > fail. > > > > > > > > In the current design of KVM in QEMU, it does a generic translation > > > > from gIOVA->gPA for the doorbell location to inject IRQ, whether VM > > > > has an accelerated IOMMU or an emulated IOMMU. > > > > > > And what happens if the translation fails because there is no mapping? > > > It should be ignored for this case and not ignored for others. > > > > It errors out and does no injection. IOW, yea, "ignored". > > "does no injection" does not sound like ignored to me.. Sorry. I think I've missed your point. The hardware path is programmed with a RMR-ed sw_msi in the host via VFIO's PCI IRQ, ignoring the gIOVA and vITS in the guest VM, even if the vPCI is programmed with a wrong gIOVA that could not be translated. KVM would always get the IRQ from HW, since the HW is programmed correctly. But if gIOVA->vITS is not mapped, i.e. gIOVA is given incorrectly, it can't inject the IRQ. (Perhaps vSMMU in this case should F_TRANSLATION to the device.) What was the meaning of "ignore" in your remarks? Thanks Nicolin