From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 4/4] drm/i915/display: shorten the intel_display_irq_regs_* function names
Date: Mon, 10 Nov 2025 22:31:52 +0200 [thread overview]
Message-ID: <aRJLuIJlD1wsIBDn@intel.com> (raw)
In-Reply-To: <ab7b409334ad0b02f531dcacbbad0f7d4a20c6f1.1762803004.git.jani.nikula@intel.com>
On Mon, Nov 10, 2025 at 09:31:39PM +0200, Jani Nikula wrote:
> Shorten the intel_display_irq_regs_* function names to the underlying
> function names with a _wl suffix for clarity.
>
> - intel_display_irq_regs_init() -> irq_init_wl()
> - intel_display_irq_regs_reset() -> irq_reset_wl()
> - intel_display_irq_regs_assert_irr_is_zero() -> assert_iir_is_zero_wl()
>
> This emphasizes the difference is the wakelock. Platforms without the
> DMC wakelock mechanism can use the non-wl versions.
These things should just get nuked. You already switched to
intel_de_{read,write}() in the previous patch, and those already
handle the wakelock stuff for you.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_irq.c | 76 +++++++++----------
> 1 file changed, 34 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index c9e7814479f6..09036cd92558 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -97,9 +97,8 @@ static void error_init(struct intel_display *display, struct i915_error_regs reg
> intel_de_posting_read(display, regs.emr);
> }
>
> -static void
> -intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs,
> - u32 imr_val, u32 ier_val)
> +static void irq_init_wl(struct intel_display *display, struct i915_irq_regs regs,
> + u32 imr_val, u32 ier_val)
> {
> intel_dmc_wl_get(display, regs.imr);
> intel_dmc_wl_get(display, regs.ier);
> @@ -112,8 +111,7 @@ intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs
> intel_dmc_wl_put(display, regs.imr);
> }
>
> -static void
> -intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs regs)
> +static void irq_reset_wl(struct intel_display *display, struct i915_irq_regs regs)
> {
> intel_dmc_wl_get(display, regs.imr);
> intel_dmc_wl_get(display, regs.ier);
> @@ -126,8 +124,7 @@ intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs
> intel_dmc_wl_put(display, regs.imr);
> }
>
> -static void
> -intel_display_irq_regs_assert_irr_is_zero(struct intel_display *display, i915_reg_t reg)
> +static void assert_iir_is_zero_wl(struct intel_display *display, i915_reg_t reg)
> {
> intel_dmc_wl_get(display, reg);
>
> @@ -1983,7 +1980,7 @@ static void _vlv_display_irq_reset(struct intel_display *display)
>
> i9xx_pipestat_irq_reset(display);
>
> - intel_display_irq_regs_reset(display, VLV_IRQ_REGS);
> + irq_reset_wl(display, VLV_IRQ_REGS);
> display->irq.vlv_imr_mask = ~0u;
> }
>
> @@ -2094,7 +2091,7 @@ static void _vlv_display_irq_postinstall(struct intel_display *display)
>
> display->irq.vlv_imr_mask = ~enable_mask;
>
> - intel_display_irq_regs_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);
> + irq_init_wl(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);
> }
>
> void vlv_display_irq_postinstall(struct intel_display *display)
> @@ -2145,10 +2142,10 @@ void gen8_display_irq_reset(struct intel_display *display)
> for_each_pipe(display, pipe)
> if (intel_display_power_is_enabled(display,
> POWER_DOMAIN_PIPE(pipe)))
> - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
> + irq_reset_wl(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
>
> - intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS);
> - intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS);
> + irq_reset_wl(display, GEN8_DE_PORT_IRQ_REGS);
> + irq_reset_wl(display, GEN8_DE_MISC_IRQ_REGS);
>
> if (HAS_PCH_SPLIT(display))
> ibx_display_irq_reset(display);
> @@ -2190,18 +2187,18 @@ void gen11_display_irq_reset(struct intel_display *display)
> for_each_pipe(display, pipe)
> if (intel_display_power_is_enabled(display,
> POWER_DOMAIN_PIPE(pipe)))
> - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
> + irq_reset_wl(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
>
> - intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS);
> - intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS);
> + irq_reset_wl(display, GEN8_DE_PORT_IRQ_REGS);
> + irq_reset_wl(display, GEN8_DE_MISC_IRQ_REGS);
>
> if (DISPLAY_VER(display) >= 14)
> - intel_display_irq_regs_reset(display, PICAINTERRUPT_IRQ_REGS);
> + irq_reset_wl(display, PICAINTERRUPT_IRQ_REGS);
> else
> - intel_display_irq_regs_reset(display, GEN11_DE_HPD_IRQ_REGS);
> + irq_reset_wl(display, GEN11_DE_HPD_IRQ_REGS);
>
> if (INTEL_PCH_TYPE(display) >= PCH_ICP)
> - intel_display_irq_regs_reset(display, SDE_IRQ_REGS);
> + irq_reset_wl(display, SDE_IRQ_REGS);
> }
>
> void gen8_irq_power_well_post_enable(struct intel_display *display,
> @@ -2219,9 +2216,9 @@ void gen8_irq_power_well_post_enable(struct intel_display *display,
> }
>
> for_each_pipe_masked(display, pipe, pipe_mask)
> - intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),
> - display->irq.de_pipe_imr_mask[pipe],
> - ~display->irq.de_pipe_imr_mask[pipe] | extra_ier);
> + irq_init_wl(display, GEN8_DE_PIPE_IRQ_REGS(pipe),
> + display->irq.de_pipe_imr_mask[pipe],
> + ~display->irq.de_pipe_imr_mask[pipe] | extra_ier);
>
> spin_unlock_irq(&display->irq.lock);
> }
> @@ -2239,7 +2236,7 @@ void gen8_irq_power_well_pre_disable(struct intel_display *display,
> }
>
> for_each_pipe_masked(display, pipe, pipe_mask)
> - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
> + irq_reset_wl(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
>
> spin_unlock_irq(&display->irq.lock);
>
> @@ -2272,7 +2269,7 @@ static void ibx_irq_postinstall(struct intel_display *display)
> else
> mask = SDE_GMBUS_CPT;
>
> - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
> + irq_init_wl(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
> }
>
> void valleyview_enable_display_irqs(struct intel_display *display)
> @@ -2334,7 +2331,7 @@ void ilk_de_irq_postinstall(struct intel_display *display)
> }
>
> if (display->platform.haswell) {
> - intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR);
> + assert_iir_is_zero_wl(display, EDP_PSR_IIR);
> display_mask |= DE_EDP_PSR_INT_HSW;
> }
>
> @@ -2345,8 +2342,8 @@ void ilk_de_irq_postinstall(struct intel_display *display)
>
> ibx_irq_postinstall(display);
>
> - intel_display_irq_regs_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask,
> - display_mask | extra_mask);
> + irq_init_wl(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask,
> + display_mask | extra_mask);
> }
>
> static void mtp_irq_postinstall(struct intel_display *display);
> @@ -2422,11 +2419,10 @@ void gen8_de_irq_postinstall(struct intel_display *display)
> if (!intel_display_power_is_enabled(display, domain))
> continue;
>
> - intel_display_irq_regs_assert_irr_is_zero(display,
> - TRANS_PSR_IIR(display, trans));
> + assert_iir_is_zero_wl(display, TRANS_PSR_IIR(display, trans));
> }
> } else {
> - intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR);
> + assert_iir_is_zero_wl(display, EDP_PSR_IIR);
> }
>
> for_each_pipe(display, pipe) {
> @@ -2434,23 +2430,20 @@ void gen8_de_irq_postinstall(struct intel_display *display)
>
> if (intel_display_power_is_enabled(display,
> POWER_DOMAIN_PIPE(pipe)))
> - intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),
> - display->irq.de_pipe_imr_mask[pipe],
> - de_pipe_enables);
> + irq_init_wl(display, GEN8_DE_PIPE_IRQ_REGS(pipe),
> + display->irq.de_pipe_imr_mask[pipe],
> + de_pipe_enables);
> }
>
> - intel_display_irq_regs_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked,
> - de_port_enables);
> - intel_display_irq_regs_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked,
> - de_misc_masked);
> + irq_init_wl(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables);
> + irq_init_wl(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked);
>
> if (IS_DISPLAY_VER(display, 11, 13)) {
> u32 de_hpd_masked = 0;
> u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
> GEN11_DE_TBT_HOTPLUG_MASK;
>
> - intel_display_irq_regs_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked,
> - de_hpd_enables);
> + irq_init_wl(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, de_hpd_enables);
> }
> }
>
> @@ -2461,17 +2454,16 @@ static void mtp_irq_postinstall(struct intel_display *display)
> u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK |
> XELPDP_TBT_HOTPLUG_MASK;
>
> - intel_display_irq_regs_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask,
> - de_hpd_enables);
> + irq_init_wl(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, de_hpd_enables);
>
> - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);
> + irq_init_wl(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);
> }
>
> static void icp_irq_postinstall(struct intel_display *display)
> {
> u32 mask = SDE_GMBUS_ICP;
>
> - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
> + irq_init_wl(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
> }
>
> void gen11_de_irq_postinstall(struct intel_display *display)
> --
> 2.47.3
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2025-11-10 20:31 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-10 19:31 [PATCH 0/4] drm/{i915, xe}/irq: clarify display and parent driver interfaces Jani Nikula
2025-11-10 19:31 ` [PATCH 1/4] drm/{i915, xe}/display: move irq calls to parent interface Jani Nikula
2025-11-10 20:31 ` [PATCH 1/4] drm/{i915,xe}/display: " Ville Syrjälä
2025-11-11 7:39 ` Jani Nikula
2025-11-10 19:31 ` [PATCH 2/4] drm/{i915, xe}/display: duplicate gen2 irq/error init/reset in display irq Jani Nikula
2025-11-10 19:31 ` [PATCH 3/4] drm/i915/display: convert the display irq interfaces to struct intel_display Jani Nikula
2025-11-10 19:31 ` [PATCH 4/4] drm/i915/display: shorten the intel_display_irq_regs_* function names Jani Nikula
2025-11-10 20:31 ` Ville Syrjälä [this message]
2025-11-11 8:07 ` Jani Nikula
2025-11-10 21:01 ` ✗ CI.checkpatch: warning for drm/{i915, xe}/irq: clarify display and parent driver interfaces Patchwork
2025-11-10 21:02 ` ✓ CI.KUnit: success " Patchwork
2025-11-10 21:17 ` ✗ CI.checksparse: warning " Patchwork
2025-11-10 21:39 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-10 21:57 ` ✓ i915.CI.BAT: " Patchwork
2025-11-11 4:43 ` ✓ i915.CI.Full: " Patchwork
2025-11-11 4:47 ` ✓ Xe.CI.Full: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aRJLuIJlD1wsIBDn@intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.