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From: Imre Deak <imre.deak@intel.com>
To: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Subject: Re: [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables
Date: Wed, 12 Nov 2025 14:58:23 +0200	[thread overview]
Message-ID: <aRSEbyFJsrIxJzro@ideak-desk> (raw)
In-Reply-To: <DM3PPF208195D8D2ED4D7B5A2AC5C6283BCE3CCA@DM3PPF208195D8D.namprd11.prod.outlook.com>

On Wed, Nov 12, 2025 at 06:10:36AM +0200, Suraj Kandpal wrote:
> > Subject: Re: [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables
> > 
> > On Tue, Nov 11, 2025 at 07:36:47AM +0200, Suraj Kandpal wrote:
> > > > + [...]
> > > > +static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> > > > +				   struct intel_encoder *encoder) {
> > > > +	int err = -ENOENT;
> > > > +
> > > > +	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> > > > +
> > > > +	/* try computed C20 HDMI tables before using consolidated tables */
> > > > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> > > > +		/* TODO: Update SSC state for HDMI as well */
> > > > +		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> > > > +
> > > > +	if (err)
> > > > +		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> > >
> > > So this is something I have been meaning to fix we should really be
> > > using the HDMI tables already defined. Computing them ourselves, that
> > > should be reserved for only when we do not have any HDMI table for the
> > > said port clock available.
> > 
> > > Also if we use the computed tables directly that means we never end up
> > > using the defined tables.
> > >
> > > SO the flow here should be
> > >
> > > err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> > >
> > > if (err && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)))
> > > 	err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> > 
> > This patch is not meant to change the logic, it simply wants to make the logic
> > clearer to the reader. What you suggest should be a separate patch
> 
> I am fine with that do you want to add that as a part of this series
> or should I send a separate Patch fixing this.

I think that change is not in the scope of this patchset, so it would be
better if you could follow up with it separately.

> Either way
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

Thanks.

> > 
> > > something like this.
> > >
> > > Regards,
> > > Suraj Kandpal
> > >
> > > > +
> > > > +	return err;
> > > >  }
> > > >
> > > >  int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > > > --
> > > > 2.34.1

  reply	other threads:[~2025-11-12 12:58 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-31 10:35 [CI 00/32] [PATCH 00/32] drm/i915/display: Add MTL+ platforms to support dpll framework Mika Kahola
2025-10-31 10:35 ` [CI 01/32] drm/i915/display: Rename TBT functions to be ICL specific Mika Kahola
2025-11-11  5:21   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 02/32] drm/i915/display: Factor out C10 msgbus access start/end helpers Mika Kahola
2025-11-11  5:26   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 03/32] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag Mika Kahola
2025-11-11  5:29   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables Mika Kahola
2025-11-11  5:36   ` Kandpal, Suraj
2025-11-11 10:02     ` Imre Deak
2025-11-12  4:10       ` Kandpal, Suraj
2025-11-12 12:58         ` Imre Deak [this message]
2025-10-31 10:35 ` [CI 05/32] drm/i915/display: Track the C20 PHY VDR state in the PLL state Mika Kahola
2025-11-11  5:43   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 06/32] drm/i915/display: Move definition of Cx0 PHY functions earlier Mika Kahola
2025-11-11  5:45   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 07/32] drm/i915/display: Add macro to get DDI port width from a register value Mika Kahola
2025-11-11  5:47   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 08/32] drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state Mika Kahola
2025-11-11  5:55   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup Mika Kahola
2025-11-11  5:56   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 10/32] drm/i915/display: Read out the Cx0 PHY SSC enabled state Mika Kahola
2025-11-12  4:13   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state Mika Kahola
2025-11-11  6:08   ` Kandpal, Suraj
2025-11-11 10:11     ` Imre Deak
2025-11-12  4:15       ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 12/32] drm/i915/display: Determine Cx0 PLL port clock " Mika Kahola
2025-11-11  6:11   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 13/32] drm/i915/display: Zero Cx0 PLL state before compute and HW readout Mika Kahola
2025-11-11  6:13   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state Mika Kahola
2025-11-11  6:17   ` Kandpal, Suraj
2025-11-11 11:14   ` Jani Nikula
2025-11-11 11:16     ` Jani Nikula
2025-11-11 12:34       ` Imre Deak
2025-10-31 10:35 ` [CI 15/32] drm/i915/display: Remove state verification Mika Kahola
2025-11-11  6:20   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 16/32] drm/i915/display: PLL information for MTL+ Mika Kahola
2025-11-12  4:19   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 17/32] drm/i915/display: Update C10/C20 state calculation Mika Kahola
2025-11-12  4:28   ` Kandpal, Suraj
2025-11-12 13:52     ` Kahola, Mika
2025-10-31 10:35 ` [CI 18/32] drm/i915/display: Compute plls for MTL+ platform Mika Kahola
2025-11-12  4:41   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 19/32] drm/i915/display: MTL+ .get_dplls Mika Kahola
2025-11-12  4:47   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 20/32] drm/i915/display: MTL+ .put_dplls Mika Kahola
2025-11-12  4:49   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 21/32] drm/i915/display: Add .update_active_dpll Mika Kahola
2025-11-12  4:50   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 22/32] drm/i915/display: Add .update_dpll_ref_clks Mika Kahola
2025-11-12  4:51   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 23/32] drm/i915/display: Add .dump_hw_state Mika Kahola
2025-11-12  5:07   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 24/32] drm/i915/display: Add .compare_hw_state Mika Kahola
2025-11-12  5:10   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 25/32] drm/i915/display: Add .get_hw_state to MTL+ platforms Mika Kahola
2025-11-12  5:14   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 26/32] drm/i915/display: Add .get_freq " Mika Kahola
2025-11-12  5:19   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 27/32] drm/i915/display: Add .crtc_get_dpll hook Mika Kahola
2025-11-12  5:20   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 28/32] drm/i915/display: PLL verify debug state print Mika Kahola
2025-11-12  5:27   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 29/32] drm/i915/display: Add .enable_clock on DDI for MTL+ platforms Mika Kahola
2025-11-12  5:32   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 30/32] drm/i915/display: Get configuration for C10 and C20 Mika Kahola
2025-10-31 10:35 ` [CI 31/32] drm/i915/display: Add Thunderbolt support Mika Kahola
2025-10-31 10:35 ` [CI 32/32] drm/i915/display: Enable dpll framework for MTL+ Mika Kahola
2025-11-12  5:39   ` Kandpal, Suraj
2025-10-31 12:48 ` ✗ CI.checkpatch: warning for drm/i915/display: Add MTL+ platforms to support dpll framework (rev2) Patchwork
2025-10-31 12:49 ` ✓ CI.KUnit: success " Patchwork
2025-10-31 13:04 ` ✗ CI.checksparse: warning " Patchwork
2025-10-31 13:54 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-31 15:03 ` ✓ i915.CI.BAT: " Patchwork
2025-10-31 19:57 ` ✗ i915.CI.Full: failure " Patchwork
2025-11-01  0:15 ` ✗ Xe.CI.Full: " Patchwork

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