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Date: Fri, 21 Nov 2025 09:35:16 +0100 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: Jan Beulich Cc: Andrew Cooper , xen-devel@lists.xenproject.org Subject: Re: [PATCH 06/12] x86/i8259: redo workaround for AMD spurious PIC interrupts Message-ID: References: <20251120090637.25087-1-roger.pau@citrix.com> <20251120095826.25782-1-roger.pau@citrix.com> <126dc8bb-4f89-4a40-b39a-1b09d78b3eac@suse.com> Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <126dc8bb-4f89-4a40-b39a-1b09d78b3eac@suse.com> X-ClientProxiedBy: MN0P223CA0024.NAMP223.PROD.OUTLOOK.COM (2603:10b6:208:52b::31) To CH7PR03MB7860.namprd03.prod.outlook.com (2603:10b6:610:24e::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH7PR03MB7860:EE_|BN9PR03MB5961:EE_ X-MS-Office365-Filtering-Correlation-Id: ab295cfa-4795-4de4-1183-08de28d8e72d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?MjR3SXRpcHRTMU5pbko0c21aRTlMMlhIaFBXR0UvUnVRb0tscHpwZm8vOTFM?= =?utf-8?B?TDgrVERYc2NYV29CL2tWTlg2RnVITHpGb0JwMklYMzlndnc2N0FsaS91allO?= =?utf-8?B?YXdPWlRDcUwwajl5OG5FTEVwdUhlY1VQNEcxTGZ3b3VXS20yYWtGMmQ1RVRl?= =?utf-8?B?K3ZjcFJEWER0VnZNRHkzUUkyTHludmVGT1dpVXhKbFowaUpqTERXbFlZNjlO?= =?utf-8?B?NG84cy8rVnhwYjdvNGZyWHd3V0NXT0JEMk1MOUZIa0toVmUxL0dQem1GcWtn?= =?utf-8?B?WmNxV083a3BvSFo0YmRFS2VvN0ZCMzBEcjJuSGg5YjMzVVVSc3ZuSU1STG9s?= =?utf-8?B?cHBwcnJ0THlZeUswb1p6aFVEd0hrblJoQUxKY1VYY2JzVm02YnZpN0hXQXF3?= =?utf-8?B?SXgxazJzN1RleThZSVh5RXVOemlvN1kwV1ozT3FHMWJ2UUEvUW1ZTWI3K2x4?= =?utf-8?B?eDR2eXpVaGJQVkFDMWszL1hnaHRLeWswdXJXbXdpUWhSWHVjV1lrU3g1ajRr?= =?utf-8?B?Q1lBVW9OSlVwN3lxb3JIMEJncWdYZytxUXV5MGRXZTFPSWRPZk1vL1pHYjhl?= =?utf-8?B?RmtHWGZ6b2hHTWVGZktXa2hnanJ1dTJaZVdmdFlQL3BaTU1URStKc3hUbGIz?= =?utf-8?B?SHFnYmsrdFQrRDZITVRORHQzb2p1RDZRNmkxRWJHWHFuZ3BrSHlUS1JQSFBT?= =?utf-8?B?bHJqU3Y2OXM5L3pWUFN1Y1g4ME1odVhJVG9lRk42eDRma09pMU1wdTJYLzYw?= =?utf-8?B?TzI3cmwxRWYzVFVYWGMxaVBiK2grcGY1RWdhbkkxOVFxVStaSDhtMy9JS0NJ?= =?utf-8?B?NGhYMnV4NHp6ZUhBaFZxOHY1NnExSmoxbktqVHlHSUtQOEwySHpRLy9xeWZ6?= =?utf-8?B?UG04andYMWhVUjRtdForY3RVelpwdk91dDVKVE1FUmp5N1kwUTZGUnBWbnl6?= =?utf-8?B?TW9Pc21BUlZpS1RpUk5uL0xOYTlqeXQyVmtNSUptT0VmYldWTUh1c0dkZWJQ?= =?utf-8?B?VTRtTHFWYVM1b08rbmJ2Y211aXJWWXZLaG9LRmwyaU92OTFwT1VGRVFnWktD?= =?utf-8?B?d2M0R2huWks4UGl1UFlOdUVTSmcvQS96NHdBYzZWRzNXYUJid2w4VnRSeWVV?= =?utf-8?B?eWpFWEVJOExPTlNVTEhNS29DV2R5TEZVWGc4RS9mY2I3Q0ZQVmw2eUFYaXc2?= =?utf-8?B?WTQ5clpoK3l6QUY3QStNRDB3SmxtYllaNmxrNHRodE9aQk5EdlNIQUVsRDJG?= =?utf-8?B?clBzWlNIQkVYVEUrWUZ2dzlvS3JuY044RHBzMm9NdEUrWlJvTVNCT2oyN0ZD?= =?utf-8?B?ajBsS1RpMWtKVkdtWC9VL3g4WE0xZ1NqVjZZdHNabWlwUWhsRFpydGttdmty?= =?utf-8?B?SFBFL08yZGp2eUdPeGJvVWlNQlkwckwvTkdTTmdHYzZFVVk5cjI4RWJGOFVm?= =?utf-8?B?d1lvWHkvTUR2ajVISGt1bzRoaURmSjFhemo1UG84TUdlUW9YbmlzZlg4QmZS?= =?utf-8?B?UUs1VFBSMTdEM0xjSitKaVNqNzJKaU45MVgrWkJpTVJRUVRTVFk0eE96NER5?= =?utf-8?B?eE51THJoUlppbEREcS9uZldheUJMVW1JQjdKbjdwSVJxTEorQ2dUa3hWNC84?= =?utf-8?B?bEhvMktvbHpoTDBvTVgrZ1pEQ0F5aFFPMlpRKzljNzhwdVNZZmMvcDd2L2FT?= =?utf-8?B?d2dPcGNXWWxyUmtEV25BSGNTbzNVOWNBekRTMnpjMjRJUU1mZDhhK0JpWmw1?= =?utf-8?B?RUtnWVV5MzY3RmpLSGxpU0RhOUVZeE03NTkrVGdIbUE2SlJpUDhVZld2SENp?= =?utf-8?B?ajJEb0VaS3dmTnBRUm83c2dEaWFUL1A3YUllSU8xSkdqOUVqeVRoTm5CNEZM?= =?utf-8?B?WDc4ckVOVVFHQ0p0Z1ZkRjRSbjdmRmx5T2N5eWl5WXFCVkloZHozeDI0d2xa?= =?utf-8?Q?FLAJ7gHOrGOgJK3C/ZQPDbBEHaM8Mgtn?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH7PR03MB7860.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(376014);DIR:OUT;SFP:1101; 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> > > > /* > > - * The interrupt affinity logic never targets interrupts to offline > > - * CPUs, hence it's safe to use cpumask_all here. > > - * > > * Legacy PIC interrupts are only targeted to CPU0, but depending on > > * the platform they can be distributed to any online CPU in hardware. > > - * Note this behavior has only been observed on AMD hardware. In order > > - * to cope install all active legacy vectors on all CPUs. > > - * > > - * IO-APIC will change the destination mask if/when taking ownership of > > - * the interrupt. > > + * Note this behavior has only been observed on AMD hardware. Set the > > + * target CPU as expected here, and cope with the possibly spurious > > + * interrupts in do_IRQ(). This behavior has only been observed > > + * during AP bringup. > > */ > > - cpumask_copy(desc->arch.cpu_mask, > > - (boot_cpu_data.x86_vendor & > > - (X86_VENDOR_AMD | X86_VENDOR_HYGON) ? &cpumask_all > > - : cpumask_of(cpu))); > > + cpumask_copy(desc->arch.cpu_mask, cpumask_of(cpu)); > > desc->arch.vector = LEGACY_VECTOR(irq); > > } > > Doesn't this collide with what setup_vector_irq() does (see also patch 04)? If > you don't set all bits here, not all CPUs will have the vector_irq[] slot set > correctly for do_IRQ() to actually be able to associate the vector with the > right IRQ. For the AMD workaround I've only ever saw the spurious vector triggering on CPUs different than the BSP at bringup, I don't think we strictly need to bind all legacy vectors on all possible CPUs. Well behaved PIC interrupts will only target the BSP, and that's properly setup. Thanks, Roger.