From: Zhao Liu <zhao1.liu@intel.com>
To: Ewan Hai <ewanhai-oc@zhaoxin.com>
Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, ewanhai@zhaoxin.com,
cobechen@zhaoxin.com
Subject: Re: [PATCH v2 3/4] target/i386: Introduce Zhaoxin Shijidadao-Client CPU model
Date: Tue, 25 Nov 2025 15:35:21 +0800 [thread overview]
Message-ID: <aSVcOX5WvJYjIEbM@intel.com> (raw)
In-Reply-To: <20251027102139.270662-4-ewanhai-oc@zhaoxin.com>
> + /*
> + * TODO: When the Linux kernel introduces other existing definitions
> + * for this leaf, remember to update the definitions here.
> + */
This TODO seems a bit vague; it's best to explicitly list the existing
features that are currently missing. Otherwise, maintainers won't be
able to understand or clean up this TODO either.
> + .features[FEAT_C000_0001_EDX] =
> + CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM |
> + CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE |
> + CPUID_C000_0001_EDX_ACE2 |
> + CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT |
> + CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE,
...
> + .model_id = "Zhaoxin Shijidadao-Client Processor",
> + .cache_info = &shijidadao_cache_info,
> + .versions = (X86CPUVersionDefinition[]) {
> + { .version = 1 },
> + {
> + .version = 2,
> + .note = "with more XSAVE features",
it's better to mention "without smap" as well.
(Based based on my personal experience, the absence of SMAP seems a bit
odd. Could it be a hardware bug in a specific stepping?)
> + .props = (PropValue[]) {
> + { "xsavec", "on" },
> + { "xgetbv1", "on" },
> + { "xsaves", "on"},
> + { "vmx-xsaves", "on"},
> + { "smap", "off" },
> + { /* end of list */ }
> + },
> + },
BTW, if the differences aren't too significant, is it possible to merge
the server and client models? :)
Thanks,
Zhao
next prev parent reply other threads:[~2025-11-25 7:11 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-27 10:21 [PATCH v2 0/4] target/i386: Add support for Zhaoxin Shijidadao vCPU models Ewan Hai
2025-10-27 10:21 ` [PATCH v2 1/4] target/i386: Add an option in X86CPUDefinition to control CPUID 0x1f Ewan Hai
2025-11-25 7:37 ` Zhao Liu
2025-10-27 10:21 ` [PATCH v2 2/4] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs Ewan Hai
2025-11-25 7:15 ` Zhao Liu
2025-10-27 10:21 ` [PATCH v2 3/4] target/i386: Introduce Zhaoxin Shijidadao-Client CPU model Ewan Hai
2025-11-25 7:35 ` Zhao Liu [this message]
2025-11-25 8:57 ` Ewan Hai
2025-12-15 9:03 ` Zhao Liu
2026-01-05 10:11 ` Ewan Hai
2026-01-07 3:55 ` Zhao Liu
2026-01-07 3:36 ` Ewan Hai
2025-10-27 10:21 ` [PATCH v2 4/4] target/i386: Introduce Zhaoxin Shijidadao-Server " Ewan Hai
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