Re: [PATCH v5 3/7] iommu/arm-smmu-v3: Introduce a per-domain arm_smmu_invs array

[Nicolin Chen <nicolinc@nvidia.com>]

On Mon, Nov 24, 2025 at 07:03:33PM -0400, Jason Gunthorpe wrote:
> On Mon, Nov 24, 2025 at 02:41:15PM -0800, Nicolin Chen wrote:
> > On Mon, Nov 24, 2025 at 09:42:31PM +0000, Will Deacon wrote:
> > > On Sat, Nov 08, 2025 at 12:08:04AM -0800, Nicolin Chen wrote:
> > 
> > > > +EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_merge);
> > > 
> > > There's nothing really SMMU-specific about this data structure manipulation.
> > > Do you think we can abstract the invalidation array concept into a library
> > > which other IOMMU drivers could use too?
> > 
> > Yea, I am trying to shift to that at this moment, hopefully to
> > combine the iotlb tag (asid/vmid) allocation as well. We do see
> > it could be quite useful in AMD driver already.
> 
> I do want to see this, but also without doing work on the other
> drivers to integrate something it will be hard to design.
> 
> My preference is to get the basic system agreed here in ARM and then
> move to a generalization. There is quite a bit of work needed in the
> other drivers before they could use it - which makes me worry it might
> never happen anyhow. riscv is probably the closest, followed by intel.

OK. I'm sending a v6, keeping it as-is. I think this itself could
be merged as an introductory series, so long as Will is okay with
it.

Meanwhile, I will spare a bit more time to organize the ASID/VMID
allocation (part-2) to hopefully integrate into the array helpers
that will be required to share a nesting parent domain.

After that, we may think of shifting it to a core library.

Thanks
Nicolin