Re: [PATCH] drm/xe: Increase log level for unhandled page faults

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Thu, Dec 18, 2025 at 02:37:45PM -0800, Matthew Brost wrote:
> Set the kernel log level for unhandled page faults to match the log
> level (info) for engine resets. Currently, dmesg output can be confusing
> because it shows an engine reset without indicating the page fault that
> caused it. Without this change, the GuC log must be examined to
> determine the source of the engine reset.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_guc_submit.c | 12 +++++-----
>  drivers/gpu/drm/xe/xe_pagefault.c  | 36 +++++++++++++++---------------
>  2 files changed, 24 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index 43fd2069f9b2..259c4e1dcae7 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> @@ -3159,13 +3159,13 @@ int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg,
>  	 * See bspec 54047 and 72187 for details.
>  	 */
>  	if (type != XE_GUC_CAT_ERR_TYPE_INVALID)
> -		xe_gt_dbg(gt,
> -			  "Engine memory CAT error [%u]: class=%s, logical_mask: 0x%x, guc_id=%d",
> -			  type, xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id);
> +		xe_gt_info(gt,
> +			   "Engine memory CAT error [%u]: class=%s, logical_mask: 0x%x, guc_id=%d",
> +			   type, xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id);
>  	else
> -		xe_gt_dbg(gt,
> -			  "Engine memory CAT error: class=%s, logical_mask: 0x%x, guc_id=%d",
> -			  xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id);
> +		xe_gt_info(gt,
> +			   "Engine memory CAT error: class=%s, logical_mask: 0x%x, guc_id=%d",
> +			   xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id);
>  
>  	trace_xe_exec_queue_memory_cat_error(q);
>  
> diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
> index afb06598b6e1..6bee53d6ffc3 100644
> --- a/drivers/gpu/drm/xe/xe_pagefault.c
> +++ b/drivers/gpu/drm/xe/xe_pagefault.c
> @@ -223,22 +223,22 @@ static bool xe_pagefault_queue_pop(struct xe_pagefault_queue *pf_queue,
>  
>  static void xe_pagefault_print(struct xe_pagefault *pf)
>  {
> -	xe_gt_dbg(pf->gt, "\n\tASID: %d\n"
> -		  "\tFaulted Address: 0x%08x%08x\n"
> -		  "\tFaultType: %d\n"
> -		  "\tAccessType: %d\n"
> -		  "\tFaultLevel: %d\n"
> -		  "\tEngineClass: %d %s\n"
> -		  "\tEngineInstance: %d\n",
> -		  pf->consumer.asid,
> -		  upper_32_bits(pf->consumer.page_addr),
> -		  lower_32_bits(pf->consumer.page_addr),
> -		  pf->consumer.fault_type,
> -		  pf->consumer.access_type,
> -		  pf->consumer.fault_level,
> -		  pf->consumer.engine_class,
> -		  xe_hw_engine_class_to_str(pf->consumer.engine_class),
> -		  pf->consumer.engine_instance);
> +	xe_gt_info(pf->gt, "\n\tASID: %d\n"
> +		   "\tFaulted Address: 0x%08x%08x\n"
> +		   "\tFaultType: %d\n"
> +		   "\tAccessType: %d\n"
> +		   "\tFaultLevel: %d\n"
> +		   "\tEngineClass: %d %s\n"
> +		   "\tEngineInstance: %d\n",
> +		   pf->consumer.asid,
> +		   upper_32_bits(pf->consumer.page_addr),
> +		   lower_32_bits(pf->consumer.page_addr),
> +		   pf->consumer.fault_type,
> +		   pf->consumer.access_type,
> +		   pf->consumer.fault_level,
> +		   pf->consumer.engine_class,
> +		   xe_hw_engine_class_to_str(pf->consumer.engine_class),
> +		   pf->consumer.engine_instance);
>  }
>  
>  static void xe_pagefault_queue_work(struct work_struct *w)
> @@ -260,8 +260,8 @@ static void xe_pagefault_queue_work(struct work_struct *w)
>  		err = xe_pagefault_service(&pf);
>  		if (err) {
>  			xe_pagefault_print(&pf);
> -			xe_gt_dbg(pf.gt, "Fault response: Unsuccessful %pe\n",
> -				  ERR_PTR(err));
> +			xe_gt_info(pf.gt, "Fault response: Unsuccessful %pe\n",
> +				   ERR_PTR(err));
>  		}
>  
>  		pf.producer.ops->ack_fault(&pf, err);
> -- 
> 2.34.1
>