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From: Niklas Cassel <cassel@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: "Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Frank Li" <Frank.Li@nxp.com>,
	"Damien Le Moal" <dlemoal@kernel.org>,
	"Koichiro Den" <den@valinux.co.jp>,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI: dwc: ep: Cache MSI outbound iATU mapping
Date: Mon, 22 Dec 2025 12:11:07 +0100	[thread overview]
Message-ID: <aUknSzSpNxLeEN5o@ryzen> (raw)
In-Reply-To: <s5mbvhnummcegksauc7kyb2442ao27dwc63gyryetuvxojnxfj@a67nopel52tx>

On Mon, Dec 22, 2025 at 03:28:30PM +0530, Manivannan Sadhasivam wrote:
> 
> > Use the MSIX doorbell method which will not use iATU at all,
> > dw_pcie_ep_raise_msix_irq_doorbell().
> > 
> 
> I think this is the safe bet since this feature doesn't seem like an optional
> one.
> 
> Niklas, if you can just fix MSI in this patch and leave out MSI-X for the vendor
> drivers to transition to doorbell, I'm OK to merge it. Otherwise, I don't know
> how you can reliably fix MSI-X generation with AXI slave interface.

FWIW, I did try to simply change:

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 8f2cc1ef25e3..00770f9786e3 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -319,7 +319,8 @@ static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
        case PCI_IRQ_MSI:
                return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
        case PCI_IRQ_MSIX:
-               return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
+               return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
+                                                         interrupt_num);
        default:
                dev_err(pci->dev, "UNKNOWN IRQ type\n");
        }


For the pcie-dw-rockchip driver, but it is not working:
[  130.042849] nvme nvme0: I/O tag 0 (1000) QID 0 timeout, completion polled

Without this change, things work.

Perhaps this feature is not an optional one, but at least we will require
more changes than a simple one liner.


Kind regards,
Niklas

  parent reply	other threads:[~2025-12-22 11:11 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-10  7:13 [PATCH] PCI: dwc: ep: Cache MSI outbound iATU mapping Niklas Cassel
2025-12-22  8:19 ` Krishna Chaitanya Chundru
2025-12-22  8:36   ` Niklas Cassel
2025-12-22  8:42     ` Krishna Chaitanya Chundru
2025-12-22  8:49       ` Niklas Cassel
2025-12-22  9:58   ` Manivannan Sadhasivam
2025-12-22 10:42     ` Niklas Cassel
2025-12-22 11:11     ` Niklas Cassel [this message]
2025-12-22 11:19       ` Manivannan Sadhasivam
2025-12-22 12:23       ` Krishna Chaitanya Chundru
2025-12-22 13:00         ` Niklas Cassel
2025-12-23  1:12           ` Shawn Lin
2025-12-23  4:35             ` Krishna Chaitanya Chundru
2025-12-23  6:23               ` Shawn Lin
2025-12-23  7:12                 ` Niklas Cassel
2026-01-05 11:06                 ` Niklas Cassel
2026-01-06  1:37                   ` Shawn Lin

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