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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Dec 2025 19:07:29.9389 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23eef60d-b9e5-457c-723d-08de470d8396 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4076 Received-SPF: permerror client-ip=2a01:111:f403:c112::5; envelope-from=nicolinc@nvidia.com; helo=CY7PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Wed, Dec 10, 2025 at 01:37:26PM +0000, Shameer Kolothum wrote: > +void tegra241_cmdqv_init(SMMUv3State *s) > +{ > + SysBusDevice *sbd = SYS_BUS_DEVICE(OBJECT(s)); > + Tegra241CMDQV *cmdqv; > + > + if (!s->tegra241_cmdqv) { > + return; > + } Maybe g_assert? > +typedef struct Tegra241CMDQV { > + struct iommu_viommu_tegra241_cmdqv cmdqv_data; > + SMMUv3State *smmu; I see all the cmdqv functions want "smmu->s_accel", so maybe store "s_accel" instead? > +#ifdef CONFIG_TEGRA241_CMDQV > +bool tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, > + uint32_t *out_viommu_id, Error **errp); > +void tegra241_cmdqv_init(SMMUv3State *s); > +#else > +static inline void tegra241_cmdqv_init(SMMUv3State *s) > +{ > +} > +static inline bool > +tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, > + uint32_t *out_viommu_id, Error **errp) > +{ > + return true; Should it return false? > index 2d4970fe19..8e56e480a0 100644 > --- a/include/hw/arm/smmuv3.h > +++ b/include/hw/arm/smmuv3.h > @@ -73,6 +73,9 @@ struct SMMUv3State { > bool ats; > uint8_t oas; > bool pasid; > + /* Support for NVIDIA Tegra241 SMMU CMDQV extension */ > + struct Tegra241CMDQV *cmdqv; > + bool tegra241_cmdqv; tegra241_cmdqv is a Property, so it has to stay with SMMUv3State. But "struct Tegra241CMDQV *cmdqv" might be in the SMMUv3AccelState? Nicolin