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Tue, 30 Dec 2025 10:23:48 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 30 Dec 2025 10:23:48 -0800 Received: from Asurada-Nvidia (10.127.8.9) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Tue, 30 Dec 2025 10:23:47 -0800 Date: Tue, 30 Dec 2025 10:23:45 -0800 From: Nicolin Chen To: Shameer Kolothum CC: "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "eric.auger@redhat.com" , "peter.maydell@linaro.org" , Nathan Chen , Matt Ochs , Jason Gunthorpe , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , Krishnakant Jaju Subject: Re: [RFC PATCH 15/16] hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT Message-ID: References: <20251210133737.78257-1-skolothumtho@nvidia.com> <20251210133737.78257-16-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024)(13003099007)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2025 18:24:03.4209 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5c8abdc-be62-4831-2118-08de47d09c58 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044EE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4058 Received-SPF: permerror client-ip=2a01:111:f403:c10d::1; envelope-from=nicolinc@nvidia.com; helo=SN4PR2101CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Tue, Dec 30, 2025 at 10:11:20AM -0800, Nicolin Chen wrote: > On Tue, Dec 30, 2025 at 02:13:12AM -0800, Shameer Kolothum wrote: > > > > > > > -----Original Message----- > > > From: Nicolin Chen > > > Sent: 29 December 2025 20:11 > > > To: Shameer Kolothum > > > Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org; > > > eric.auger@redhat.com; peter.maydell@linaro.org; Nathan Chen > > > ; Matt Ochs ; Jason Gunthorpe > > > ; jonathan.cameron@huawei.com; > > > zhangfei.gao@linaro.org; zhenzhong.duan@intel.com; Krishnakant Jaju > > > > > > Subject: Re: [RFC PATCH 15/16] hw/arm/virt-acpi: Advertise Tegra241 > > > CMDQV nodes in DSDT > > > > > > On Wed, Dec 10, 2025 at 01:37:36PM +0000, Shameer Kolothum wrote: > > > > +static int smmuv3_cmdqv_devices(Object *obj, void *opaque) > > > > +{ > > > > + VirtMachineState *vms = VIRT_MACHINE(qdev_get_machine()); > > > > + GArray *sdev_blob = opaque; > > > > + PlatformBusDevice *pbus; > > > > + AcpiSMMUv3Dev sdev; > > > > + SysBusDevice *sbdev; > > > > + > > > > + if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) { > > > > + return 0; > > > > + } > > > > + > > > > + if (!object_property_get_bool(obj, "tegra241-cmdqv", NULL)) { > > > > + return 0; > > > > + } > > > > + > > > > + pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); > > > > + sbdev = SYS_BUS_DEVICE(obj); > > > > + sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 1); > > > > + sdev.base += vms->memmap[VIRT_PLATFORM_BUS].base; > > > > + sdev.irq = platform_bus_get_irqn(pbus, sbdev, NUM_SMMU_IRQS); > > > > + sdev.irq += vms->irqmap[VIRT_PLATFORM_BUS]; > > > > + sdev.irq += ARM_SPI_BASE; > > > > + g_array_append_val(sdev_blob, sdev); > > > > + return 0; > > > > > > This is pre-building SMMU's IORT nodes right? Maybe a different > > > naming? And can be shared with the existing iort_smmuv3_devices? > > > > Not really, if you are referring about this patch here, > > https://github.com/NVIDIA/QEMU/commit/cc3b65e6a49a9b7addf44b377d4ef1de99bfee3f > > Yes. I am talking about this. But you are actually pre-building an > ACPI SMMU device array here. So, my question wasn't accurate.. > > > I didn’t find a clean way to store the pre-built smmuv3_devs other than > > placing them in struct AcpiBuildTables. It’s not clear we gain much by > > restructuring things to populate and store them separately. At best, > > it might slightly improve boot time, and if that becomes important we > > can always add it as an optimization later. > > > > This patch enumerates SMMUv3 accel instances with CMDQV separately, uses > > that information to build the DSDT, and then frees the device array. > > Oh, I missed the g_array_free() in acpi_dsdt_add_tegra241_cmdqv(). > > Let's have a note inline and copy to the commit message too. > > > > We do so, because we need to link CMDQV's DSDT node to the SMMU's > > > IORT node but it is created in build_iort() that is called after > > > build_dsdt(). > > > > Hmm..not sure I get that. Does this mean IORT has a link to DSDT? I can't find one.. > > Maybe I missed. Please let me know. > > The _UID field of the DSDT node links to the Identifier field of an > SMMU's IORT node. E.g. > > [DSDT] // Qemu builds DSDT first > CMDQV0 { > _UID = 0; > } > > [IORT] // Then builds IORT > SMMU0 { > Identifier = 0; > } > > If we are sure that the SMMU sequence is fixed every time we rebuild > the sdev array so that IORT.Identifier matches with DSDT._UID, we'd > be fine. That being said, we should probably make a node inline too. Typo: node->note > Otherwise, it would be safer to pre-build the sdev array and use the > same array in both DSDT and IORT. > > Thanks > Nicolin