From: Raag Jadav <raag.jadav@intel.com>
To: "Mallesh, Koujalagi" <mallesh.koujalagi@intel.com>
Cc: intel-xe@lists.freedesktop.org, rodrigo.vivi@intel.com,
riana.tauro@intel.com, michal.wajdeczko@intel.com,
matthew.d.roper@intel.com, umesh.nerlige.ramappa@intel.com,
soham.purkait@intel.com, anoop.c.vijay@intel.com
Subject: Re: [v1,3/4] drm/xe/sysctrl: Add system controller event support
Date: Tue, 20 Jan 2026 13:10:11 +0100 [thread overview]
Message-ID: <aW9wo2QPAPW-3ZRP@black.igk.intel.com> (raw)
In-Reply-To: <c7b76289-f2af-4ff2-b1c0-c74aeaee4f98@intel.com>
On Tue, Jan 20, 2026 at 02:16:23PM +0530, Mallesh, Koujalagi wrote:
> Hi Raag,
>
> On 16-01-2026 03:03 pm, Raag Jadav wrote:
> > System controller reports different types of events to GFX endpoint for
> > different usecases, add initial support for them. This will be further
> > extended to service those usecases.
> >
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> > drivers/gpu/drm/xe/Makefile | 1 +
> > drivers/gpu/drm/xe/xe_sysctrl.c | 7 ++
> > drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> > drivers/gpu/drm/xe/xe_sysctrl_event.c | 77 +++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 49 +++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
> > 6 files changed, 145 insertions(+)
> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> >
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index ff567fa58119..16e28cab8464 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -122,6 +122,7 @@ xe-y += xe_bb.o \
> > xe_survivability_mode.o \
> > xe_sync.o \
> > xe_sysctrl.o \
> > + xe_sysctrl_event.o \
> > xe_sysctrl_mailbox.o \
> > xe_tile.o \
> > xe_tile_sysfs.o \
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> > index 1d78916dd6ad..b5a57e2dc0d8 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> > @@ -10,6 +10,7 @@
> > #include "regs/xe_irq_regs.h"
> > #include "regs/xe_sysctrl_regs.h"
> > #include "xe_device.h"
> > +#include "xe_pm.h"
> > #include "xe_printk.h"
> > #include "xe_soc_remapper.h"
> > #include "xe_sysctrl.h"
> > @@ -30,6 +31,12 @@
> > static void xe_sysctrl_work(struct work_struct *work)
> > {
> > + struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
> > + struct xe_device *xe = container_of(sc, struct xe_device, sc);
> > +
> > + xe_pm_runtime_get(xe);
> > + xe_sysctrl_event(xe);
> > + xe_pm_runtime_put(xe);
> > }
> > static void xe_sysctrl_fini(void *arg)
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> > index 5919310b9db9..bd9acf575d14 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> > @@ -12,5 +12,6 @@ struct xe_device;
> > int xe_sysctrl_init(struct xe_device *xe);
> > void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> > +void xe_sysctrl_event(struct xe_device *xe);
> > #endif /* _XE_SYSCTRL_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > new file mode 100644
> > index 000000000000..3a860bc34db0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > @@ -0,0 +1,77 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#include "xe_assert.h"
> > +#include "xe_device.h"
> > +#include "xe_irq.h"
> > +#include "xe_pm.h"
> > +#include "xe_printk.h"
> > +#include "xe_sysctrl.h"
> > +#include "xe_sysctrl_event_types.h"
> > +#include "xe_sysctrl_mailbox.h"
> > +#include "xe_sysctrl_mailbox_types.h"
> > +
> > +static void xe_sysctrl_get_pending_event(struct xe_device *xe,
> > + struct xe_sysctrl_mailbox_command *command)
> > +{
> > + struct xe_sysctrl_event_response response;
> > + size_t len;
> > + int ret;
> > +
> > + command->data_out = &response;
> > + command->data_out_len = sizeof(response);
> > +
> > + do {
> > + memset(&response, 0, sizeof(response));
> > +
> > + ret = xe_sysctrl_send_command(xe, command, &len);
> > + if (ret || !len)
> > + return;
> > +
> > + if (len != sizeof(response))
> > + xe_err(xe, "Unexpected response length %ld\n", len);
> If we see response structure is mismatched, should either return or handle
> gracefully.
Good point. My understanding was to move forward anyway in case the error
is so critical that not handling it results in graver consequences. Let's
confirm this with arch.
Raag
> > + if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED)
> > + xe_warn(xe, "Counter threshold crossed\n");
> > + else
> > + xe_err(xe, "Unexpected event %#x\n", response.event);
> > +
> > + } while (response.count);
> > +}
> > +
> > +static void xe_sysctrl_event_request_prep(struct xe_device *xe,
> > + struct xe_sysctrl_mailbox_app_msg_hdr *header,
> > + struct xe_sysctrl_event_request *request)
> > +{
> > + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> > + struct xe_sysctrl_event_request req_data;
> > + u32 req_hdr;
> > +
> > + req_hdr = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
> > + REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
>
> We need use APP_HDR_COMMAND_MASK right?
Yep, missed it. Thanks.
Raag
> > +
> > + req_data.vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
> > + req_data.fn = PCI_FUNC(pdev->devfn);
> > +
> > + header->data = req_hdr;
> > + *request = req_data;
> > +}
> > +
> > +void xe_sysctrl_event(struct xe_device *xe)
> > +{
> > + struct xe_sysctrl_mailbox_app_msg_hdr header = {};
> > + struct xe_sysctrl_mailbox_command command = {};
> > + struct xe_sysctrl_event_request request;
> > +
> > + xe_assert(xe, !xe_pm_runtime_suspended(xe));
> > +
> > + xe_sysctrl_event_request_prep(xe, &header, &request);
> > +
> > + command.header = header;
> > + command.data_in = &request;
> > + command.data_in_len = sizeof(request);
> > +
> > + xe_sysctrl_get_pending_event(xe, &command);
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > new file mode 100644
> > index 000000000000..9c5fb95c58f7
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > @@ -0,0 +1,49 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
> > +#define _XE_SYSCTRL_EVENT_TYPES_H_
> > +
> > +#include <linux/types.h>
> > +
> > +#define XE_SYSCTRL_EVENT_DATA_LEN 68
> > +
> > +enum xe_sysctrl_event {
> > + XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 0x01,
> > +};
> > +
> > +/**
> > + * struct xe_sysctrl_event_request - Request structure for pending event
> > + */
> > +struct xe_sysctrl_event_request {
> > + /** @vector: MSI-X vector that was triggered */
> > + u32 vector;
> > + /** @fn: Function index (0-7) of PCIe device */
> > + u8 fn;
> > + /** @reserved: Reserved for future use */
> > + u16 reserved;
> > + /** @reserved2: Reserved for future use */
> > + u32 reserved2[2];
> > +} __packed;
> > +
> > +/**
> > + * struct xe_sysctrl_event_response - Response structure for pending event
> > + */
> > +struct xe_sysctrl_event_response {
> > + /** @count: Number of pending events */
> > + u32 count;
> > + /** @event: Pending event */
> > + enum xe_sysctrl_event event;
> > + /** @timestamp: Timestamp of most recent event */
> > + u64 timestamp;
> > + /** @extended: Event has extended payload */
> > + u8 extended:1;
> > + /** @reserved: Reserved for future use */
> > + u32 reserved:23;
> > + /** @data: Generic event data */
> > + u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
> > +} __packed;
> > +
> > +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > index 750b7528bab2..c6208a611c9e 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > @@ -27,6 +27,16 @@ struct xe_sysctrl_mailbox_command;
> > #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
> > FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
> > +/* Command groups */
> > +enum xe_sysctrl_group {
> > + XE_SYSCTRL_GROUP_GFSP = 0x01,
> > +};
> > +
> > +/* Commands supported by GFSP group */
> > +enum xe_sysctrl_gfsp_cmd {
> > + XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
> > +};
> > +
> > void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
> > int xe_sysctrl_send_command(struct xe_device *xe,
> > struct xe_sysctrl_mailbox_command *cmd,
next prev parent reply other threads:[~2026-01-20 12:10 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-16 9:33 [PATCH v1 0/4] Introduce Xe Correctable Error Handling Raag Jadav
2026-01-16 9:33 ` [PATCH v1 1/4] drm/xe/sysctrl: Add System Controller Raag Jadav
2026-01-16 9:33 ` [PATCH v1 2/4] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
2026-01-16 21:30 ` Matthew Brost
2026-01-17 7:13 ` Raag Jadav
2026-01-20 8:30 ` [v1,2/4] " Mallesh, Koujalagi
2026-01-20 12:05 ` Raag Jadav
2026-01-16 9:33 ` [PATCH v1 3/4] drm/xe/sysctrl: Add system controller event support Raag Jadav
2026-01-20 8:46 ` [v1,3/4] " Mallesh, Koujalagi
2026-01-20 12:10 ` Raag Jadav [this message]
2026-01-16 9:33 ` [PATCH v1 4/4] drm/xe/ras: Introduce correctable error handling Raag Jadav
2026-01-20 8:51 ` [v1,4/4] " Mallesh, Koujalagi
2026-01-20 12:17 ` Raag Jadav
2026-01-16 10:08 ` ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling Patchwork
2026-01-16 10:09 ` ✓ CI.KUnit: success " Patchwork
2026-01-16 11:02 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-16 14:25 ` ✓ Xe.CI.Full: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aW9wo2QPAPW-3ZRP@black.igk.intel.com \
--to=raag.jadav@intel.com \
--cc=anoop.c.vijay@intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=mallesh.koujalagi@intel.com \
--cc=matthew.d.roper@intel.com \
--cc=michal.wajdeczko@intel.com \
--cc=riana.tauro@intel.com \
--cc=rodrigo.vivi@intel.com \
--cc=soham.purkait@intel.com \
--cc=umesh.nerlige.ramappa@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.