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From: Gregory Price <gourry@gourry.net>
To: dan.j.williams@intel.com
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
	kernel-team@meta.com, dave@stgolabs.net,
	jonathan.cameron@huawei.com, dave.jiang@intel.com,
	alison.schofield@intel.com, vishal.l.verma@intel.com,
	ira.weiny@intel.com
Subject: Re: [PATCH 1/6] drivers/cxl: add cxl_memctrl_mode and region->memctrl
Date: Mon, 12 Jan 2026 17:25:47 -0500	[thread overview]
Message-ID: <aWV06x8AnB-C6I1j@gourry-fedora-PF4VCD3F> (raw)
In-Reply-To: <696560c0979e0_20718100b8@dwillia2-mobl4.notmuch>

On Mon, Jan 12, 2026 at 12:59:44PM -0800, dan.j.williams@intel.com wrote:
> Gregory Price wrote:
> > --- a/drivers/cxl/core/core.h
> > +++ b/drivers/cxl/core/core.h
> > @@ -42,6 +42,8 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port);
> >  struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa);
> >  u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
> >  		   u64 dpa);
> > +int cxl_enable_memctrl(struct cxl_region *cxlr);
> 
> This is a "probe" operation not an "enable" in terms of runtime ABI and
> presentation that starts decorating the region. In that respect it also
> is not a "control" as much as an "operation model / driver". So no need
> for a "control" concept, i.e.:
> 
> s/CXL_CONTROL_{NONE,AUTO,DAX}/CXL_DRIVER_{NONE,AUTO,DAX}/
> s/enum cxl_memctrl_mode/enum cxl_region_driver/
> 

Ack.

> ...otherwise there is nothing in this proposal that makes me want to
> abandon the traditional meaning of a "driver" probing a "resource" in a
> certain way to make it usable with the rest of the kernel.
> 
> Rest of this looks fine. With that fixup if we are going to have a set
> of different region driver modes then the directory can be:
> 
> drivers/cxl/core/region/

Mostly I imagine we'll end up with at least 5-6 of these, and the
directory makes it clear for any new comers "This is what you must do if
you want a new region".

but if folks would rather have it directly in core/ then `git mv...` 

either way, ack.

~Gregory

  reply	other threads:[~2026-01-12 22:26 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20260113093758epcas5p10cc9749a657b8e4d32db75b8b973b67d@epcas5p1.samsung.com>
2026-01-12 16:35 ` [PATCH 0/6] CXL: Introduce memory controller abstraction and sysram controller Gregory Price
2026-01-12 16:35   ` [PATCH 1/6] drivers/cxl: add cxl_memctrl_mode and region->memctrl Gregory Price
2026-01-12 20:59     ` dan.j.williams
2026-01-12 22:25       ` Gregory Price [this message]
2026-01-13 18:00       ` Dave Jiang
2026-01-13 20:07         ` Gregory Price
2026-01-14 16:36         ` dan.j.williams
2026-01-12 21:10     ` Cheatham, Benjamin
2026-01-12 22:34       ` Gregory Price
2026-01-14 17:18     ` Jonathan Cameron
2026-01-14 18:25       ` Gregory Price
2026-01-14 18:36         ` Jonathan Cameron
2026-01-12 16:35   ` [PATCH 2/6] cxl: add sysram_region memory controller Gregory Price
2026-01-12 20:00     ` David Hildenbrand (Red Hat)
2026-01-12 22:43       ` Gregory Price
2026-01-12 21:10     ` dan.j.williams
2026-01-12 22:47       ` Gregory Price
2026-01-12 21:10     ` Cheatham, Benjamin
2026-01-12 22:55       ` Gregory Price
2026-01-13 22:34         ` Cheatham, Benjamin
2026-01-12 16:35   ` [PATCH 3/6] cxl/core/region: move pmem memctrl logic into memctrl/pmem_region Gregory Price
2026-01-12 21:10     ` Cheatham, Benjamin
2026-01-12 22:58       ` Gregory Price
2026-01-13  9:12         ` Neeraj Kumar
2026-01-12 16:35   ` [PATCH 4/6] cxl: add CONFIG_CXL_REGION_CTRL_AUTO_* build config options Gregory Price
2026-01-12 21:10     ` Cheatham, Benjamin
2026-01-12 23:05       ` Gregory Price
2026-01-13  4:31         ` dan.j.williams
2026-01-13 13:55           ` Gregory Price
2026-01-12 16:35   ` [PATCH 5/6] cxl: add CXL_REGION_SYSRAM_DEFAULT_* build options Gregory Price
2026-01-12 21:11     ` Cheatham, Benjamin
2026-01-12 23:07       ` Gregory Price
2026-01-12 16:35   ` [PATCH 6/6] cxl/sysram: disallow onlining in ZONE_NORMAL if state is movable only Gregory Price
2026-01-12 21:11     ` Cheatham, Benjamin
2026-01-12 23:14       ` Gregory Price
2026-01-13 22:35         ` Cheatham, Benjamin
2026-01-13  9:37   ` [PATCH 0/6] CXL: Introduce memory controller abstraction and sysram controller Neeraj Kumar
2026-01-13 13:33     ` Gregory Price
2026-01-15 18:43   ` Alejandro Lucero Palau
2026-01-15 18:56     ` Gregory Price

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