Re: [PATCH 0/7] Implement CPU frequency scaling for TH1520

From: Drew Fustini <fustini@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: Yao Zi <ziyao@disroot.org>, Yao Zi <me@ziyao.cc>,
	Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Icenowy Zheng <uwu@icenowy.me>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	Han Gao <rabenda.cn@gmail.com>, Han Gao <gaohan@iscas.ac.cn>
Subject: Re: [PATCH 0/7] Implement CPU frequency scaling for TH1520
Date: Wed, 14 Jan 2026 17:50:13 -0800	[thread overview]
Message-ID: <aWhH1aFUIieN4zVj@x1> (raw)
In-Reply-To: <aUWoSNI2mFaPARfI@x1>

On Fri, Dec 19, 2025 at 11:32:24AM -0800, Drew Fustini wrote:
> On Thu, Nov 20, 2025 at 01:14:09PM +0000, Yao Zi wrote:
> > On TH1520 SoC, c910_clk feeds the CPU cluster. It could be glitchlessly
> > reparented to one of the two PLLs: either to cpu_pll0 indirectly through
> > c910_i0_clk, or to cpu_pll1 directly. This series fixes a bug in PLL
> > enabling code, supports rate change for PLL, and finally implements
> > frequency scaling support for c910_clk.
> > 
> > However, to achieve reliable frequency scaling, CPU voltage must be
> > adjusted together with frequency, and AON-firmware-based PMIC support
> > for TH1520 SoC is still missing in mainline. Thus PATCH 7 that fills OPP
> > table for TH1520 CPU and enables CPUfreq is only for testing purpose,
> > not intended for upstream (yet).
> > 
> > Testing is done on Lichee Pi 4A board, only operating points safe
> > to be used with the the default PMIC configuration are enabled in
> > devicetree. I've confirmed there's a performance gain when running
> > coremark and some building work compared to the case without cpufreq.
> > 
> > This series is based on next-20251120, thanks for your time and review.
> > 
> > Yao Zi (7):
> >   dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock
> >   clk: thead: th1520-ap: Poll for PLL lock and wait for stability
> >   clk: thead: th1520-ap: Add C910 bus clock
> >   clk: thead: th1520-ap: Support setting PLL rates
> >   clk: thead: th1520-ap: Add macro to define multiplexers with flags
> >   clk: thead: th1520-ap: Support CPU frequency scaling
> >   [Not For Upstream] riscv: dts: thead: Add CPU clock and OPP table for
> >     TH1520
> > 
> >  arch/riscv/boot/dts/thead/th1520.dtsi         |  35 ++
> >  drivers/clk/thead/clk-th1520-ap.c             | 350 +++++++++++++++++-
> >  .../dt-bindings/clock/thead,th1520-clk-ap.h   |   1 +
> >  3 files changed, 379 insertions(+), 7 deletions(-)
> > 
> > -- 
> > 2.51.2
> > 
> 
> Applied to thead-clk-for-next, thanks!
> 
> [1/7] dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock
>       https://git.kernel.org/fustini/c/5f352125f8a0

Conor - can I included this binding patch in my thead clk pull request
to Stephen?

Thanks,
Drew