From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20C902D5408 for ; Wed, 28 Jan 2026 13:07:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769605626; cv=none; b=emsGVAXUUFESrSfpJCImU6TpZhibRxvEw5BTMvNGz1xxThRWgNBGhk7KSazq7+fEycr4oVY27xkaZvzD5SHl2/Em+ckMmZQj51RoJGnbSiPWKaON5RJfxjj2ZrZaqjpF/yYkPt31V/Gvc5Uw2nwXd5h8NCzv9oZFwKr5cuRQZZw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769605626; c=relaxed/simple; bh=IPFhi7OpdeYhkFntk0sxSwhObzY2Rx2jaL2UMqXZCqs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=c8RcMs3Wd5VdOcj57ZcE8M4RwyajaS1yk5nGiY/FjSf3kRDvdFHLnETO1T4PGOUFMFvEhdaWWKpg7txTY8LxbQiKX63N/k2cLwWBEzHQP4WEuZzC4uQ4+QyJv8NE9XzeU4P6AD0W49rQclITWcgKThkK6D/dNz2dXgBcr4dmBmg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YzzRfdYm; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YzzRfdYm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769605625; x=1801141625; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=IPFhi7OpdeYhkFntk0sxSwhObzY2Rx2jaL2UMqXZCqs=; b=YzzRfdYmRzBhHYUQDwGSP+5zJtkHNj/t+cz/ymaU9jh9YxfZ3Sucbo0O iYF9tEb+ij2TfGpvrQJzw2FTj0tLwbAO7580CKgoFKwcrNpvUHU+ZgVEj /4t8vd80cGJ1t+NmVTiuaAWBy4DwYvjW+6PTMj3VgCbvnwq6x08zRTcpb f6DH8AFhlnFc7rEnJYORnhM7r/LAYIrocksuMfv8OiJEo1Xa9BNVCkp79 UV+lhiOoI7K/O8SjheBN9QbrHmqsHFow2L/+UJa+oXKglLDWNPHRP3eWc UfixQu/gd7xvW+3FpKVjm4EJB/SPg9snebFwU0m3SARVE5ZVrDUBJkje2 g==; X-CSE-ConnectionGUID: eNTWv6MbSDWI3N+V03/Irg== X-CSE-MsgGUID: IjwhzPLsTLCoeh+9VF9iLQ== X-IronPort-AV: E=McAfee;i="6800,10657,11684"; a="70857679" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="70857679" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2026 05:07:05 -0800 X-CSE-ConnectionGUID: UM+Ibb7yRiKOtyHNgNN/vg== X-CSE-MsgGUID: FLl9mnixTo2sbkLrxdF6Gg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="213131724" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.244.196]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2026 05:07:02 -0800 Date: Wed, 28 Jan 2026 15:07:00 +0200 From: Andy Shevchenko To: Sebastian Andrzej Siewior Cc: linux-kernel@vger.kernel.org, Thomas Gleixner , Charles Keepax , Lee Jones , patches@opensource.cirrus.com, Mark Brown Subject: Re: [PATCH v2 15/20] mfd: wm8350-core: Use IRQF_ONESHOT Message-ID: References: <20260128095540.863589-1-bigeasy@linutronix.de> <20260128095540.863589-16-bigeasy@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260128095540.863589-16-bigeasy@linutronix.de> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Wed, Jan 28, 2026 at 10:55:35AM +0100, Sebastian Andrzej Siewior wrote: > Using a threaded interrupt without a dedicated primary handler mandates > the IRQF_ONESHOT flag to mask the interrupt source while the threaded > handler is active. Otherwise the interrupt can fire again before the > threaded handler had a chance to run. > > Mark explained that this should not happen with this hardware since it > is a slow irqchip which is behind an I2C/ SPI bus but the IRQ-core will > refuse to accept such a handler. > > Set IRQF_ONESHOT so the interrupt source is masked until the secondary > handler is done. Reviewed-by: Andy Shevchenko -- With Best Regards, Andy Shevchenko