Re: [PATCH] docs: simplify DiamondRapids CPU docs

[Zhao Liu <zhao1.liu@intel.com>]

On Wed, Feb 11, 2026 at 06:00:21PM +0000, Daniel P. Berrangé wrote:
> Date: Wed, 11 Feb 2026 18:00:21 +0000
> From: "Daniel P. Berrangé" <berrange@redhat.com>
> Subject: [PATCH] docs: simplify DiamondRapids CPU docs
> 
> This aligns the first line of the docs with the style used for previous
> CPU models, and simplifies the text in the remaining docs.
> 
> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
> ---
>  docs/system/cpu-models-x86.rst.inc | 16 ++++++----------
>  1 file changed, 6 insertions(+), 10 deletions(-)
> 
> diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc
> index 3605d05a8c..9d4486c978 100644
> --- a/docs/system/cpu-models-x86.rst.inc
> +++ b/docs/system/cpu-models-x86.rst.inc
> @@ -72,17 +72,13 @@ compatibility is required, use the newest CPU model that is compatible
>  across all desired hosts.
>  
>  ``DiamondRapids``
> -    Intel Xeon Processor.
> +    Intel Xeon Processor (DiamondRapids, 2025)

Maybe 2026? I think the year should be the release data instead of patch
data.

> -    Diamond Rapids product has a topology which differs from previous Xeon
> -    products. It does not support SMT, but instead features a dual core
> -    module (DCM) architecture. It also has core building blocks (CBB - die
> -    level in CPU topology). The cache hierarchy is organized as follows:
> -    L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per
> -    CBB. This cache topology can be emulated for DiamondRapids CPU model
> -    using the smp-cache configuration as shown below:
> -
> -    Example:
> +    This does not include SMT but allows the module (dual core module
> +    - DCM) and die (core building block - CBB) topology levels. The
> +    cache hierarchy is L1 i/d cache per thread, L2 cache per module,
> +    and L3 cache per die, which can be emulated using the smp-cache
> +    option:

Otherwise, look good to me, and thanks!

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Regards,
Zhao