From: Max Chou <max.chou@sifive.com>
To: "Sébastien Michelland" <sebastien.michelland@inria.fr>
Cc: qemu-devel@nongnu.org, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-riscv@nongnu.org,
Jean-Michel Gorius <jean-michel.gorius@irisa.fr>
Subject: Re: [PATCH v2] target/riscv: fix require_rvv passing on non-RVV CPUs
Date: Fri, 6 Feb 2026 01:00:45 +0800 [thread overview]
Message-ID: <aYTKYkBT7kWlcdpx@sifive.com> (raw)
In-Reply-To: <20260205125255.1219082-1-sebastien.michelland@inria.fr>
On 2026-02-05 13:52, Sébastien Michelland wrote:
> @@ -153,7 +153,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
>
> #ifdef CONFIG_USER_ONLY
> fs = EXT_STATUS_DIRTY;
> - vs = EXT_STATUS_DIRTY;
> + vs = riscv_has_ext(env, RVV) ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
> #else
> flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
Hi Sébastien,
This v2 is good, but there’s a potential bug when users enable embedded
vector extensions (e.g., ZveXX) that aren’t standard RVV.
I suggest that we replace the RVV check with a check on the Zve32x,
which will be implied by all embedded vector extensions and standard
RVV.
vs = cpu->cfg.ext_zve32x ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
rnax
prev parent reply other threads:[~2026-02-05 17:01 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-05 12:52 [PATCH v2] target/riscv: fix require_rvv passing on non-RVV CPUs Sébastien Michelland
2026-02-05 17:00 ` Max Chou [this message]
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