All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Daniel P. Berrangé" <berrange@redhat.com>
To: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
	"cfu@mips.com" <cfu@mips.com>, "mst@redhat.com" <mst@redhat.com>,
	"marcel.apfelbaum@gmail.com" <marcel.apfelbaum@gmail.com>,
	"dbarboza@ventanamicro.com" <dbarboza@ventanamicro.com>,
	"philmd@linaro.org" <philmd@linaro.org>,
	"alistair23@gmail.com" <alistair23@gmail.com>,
	"thuth@redhat.com" <thuth@redhat.com>
Subject: Re: [PATCH v2 01/16] meson: Add BE RISCV targets
Date: Wed, 25 Feb 2026 12:27:19 +0000	[thread overview]
Message-ID: <aZ7qp05kxbU7diac@redhat.com> (raw)
In-Reply-To: <20260225102016.200654-2-djordje.todorovic@htecgroup.com>

On Wed, Feb 25, 2026 at 10:20:25AM +0000, Djordje Todorovic wrote:
> Add options to compile riscv64be-softmmu and riscv32be-softmmu
> ---
>  meson.build | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/meson.build b/meson.build
> index 8c6c0a9a32..41ad38d184 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -55,6 +55,11 @@ supported_cpus = ['ppc64', 's390x', 'riscv64', 'x86_64',
>  
>  cpu = host_machine.cpu_family()
>  
> +# Unify riscv64be to riscv64.
> +if cpu == 'riscv64be'
> +  cpu = 'riscv64'
> +endif
> +
>  target_dirs = config_host['TARGET_DIRS'].split()
>  
>  # type of binaries to build
> @@ -281,7 +286,7 @@ elif cpu == 'ppc64'
>  elif cpu == 'mips64'
>    kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
>  elif cpu == 'riscv64'
> -  kvm_targets = ['riscv64-softmmu']
> +  kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu', 'riscv32be-softmmu', 'riscv64be-softmmu']

The suibject says its adding "BE" targets, but this is also adding
a 32-bit little endian target.

Does KVM, actually support running riscv32 guests on a riscv64
host ?  If so, this change to add 32-bit KVM should likely be
done as its own commit separate from this big endian series.


With regards,
Daniel
-- 
|: https://berrange.com       ~~        https://hachyderm.io/@berrange :|
|: https://libvirt.org          ~~          https://entangle-photo.org :|
|: https://pixelfed.art/berrange   ~~    https://fstop138.berrange.com :|



  parent reply	other threads:[~2026-02-25 12:27 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-25 10:20 [PATCH v2 00/16] Add RISC-V big-endian target support Djordje Todorovic
2026-02-25 10:20 ` [PATCH v2 02/16] config/targets: Add BE RISCV softmmu targets Djordje Todorovic
2026-02-25 10:20 ` [PATCH v2 01/16] meson: Add BE RISCV targets Djordje Todorovic
2026-02-25 10:39   ` Thomas Huth
2026-02-25 12:05     ` Chao Liu
2026-02-25 12:30     ` Daniel P. Berrangé
2026-02-26 23:26       ` Alistair Francis
2026-02-25 12:27   ` Daniel P. Berrangé [this message]
2026-02-25 10:20 ` [PATCH v2 03/16] config/devices: Add BE riscv configs Djordje Todorovic
2026-02-25 10:20 ` [PATCH v2 05/16] hw/riscv: Ensure bootrom has correct endianess Djordje Todorovic
2026-02-25 10:20 ` [PATCH v2 06/16] hw/riscv: Ensure proper ELF endian expectation Djordje Todorovic
2026-02-27 22:44   ` Philippe Mathieu-Daudé
2026-02-25 10:20 ` [PATCH v2 04/16] target/riscv: Ensure LE instruction fetching Djordje Todorovic
2026-02-27 22:41   ` Philippe Mathieu-Daudé
2026-02-25 10:20 ` [PATCH v2 07/16] hw/riscv: Check endianness for fw_dynamic fields Djordje Todorovic
2026-02-26 23:32   ` Alistair Francis
2026-02-27 22:47     ` Philippe Mathieu-Daudé
2026-02-25 10:20 ` [PATCH v2 09/16] arch/riscv: Set UBE bit on BE target Djordje Todorovic
2026-02-27 22:51   ` Philippe Mathieu-Daudé
2026-02-25 10:20 ` [PATCH v2 08/16] config/targets: Add RISC-V userspace targets Djordje Todorovic
2026-02-27 22:50   ` Philippe Mathieu-Daudé
2026-02-25 10:20 ` [PATCH v2 11/16] linux-user/riscv: Disable vDSO for big-endian targets Djordje Todorovic
2026-02-26 23:33   ` Alistair Francis
2026-02-27 22:55     ` Philippe Mathieu-Daudé
2026-02-25 10:20 ` [PATCH v2 12/16] target/riscv: Set SBE and MBE bits at CPU reset for BE targets Djordje Todorovic
2026-02-25 10:20 ` [PATCH v2 10/16] config/targets: Add missing fields to BE linux-user targets Djordje Todorovic
2026-02-25 10:20 ` [PATCH v2 15/16] hw/virtio: Use DEVICE_LITTLE_ENDIAN for virtio-mmio legacy ops Djordje Todorovic
2026-02-25 10:20 ` [PATCH v2 13/16] target/riscv: Fix PTE A/D atomic update endianness Djordje Todorovic
2026-02-27 23:00   ` Philippe Mathieu-Daudé
2026-02-25 10:20 ` [PATCH v2 14/16] target/riscv: Use MO_LE for instruction fetch Djordje Todorovic
2026-02-27 22:57   ` Philippe Mathieu-Daudé
2026-02-25 10:20 ` [PATCH v2 16/16] qapi: Add riscv32be and riscv64be to SysEmuTarget Djordje Todorovic
2026-02-25 11:39 ` [PATCH v2 00/16] Add RISC-V big-endian target support Mohamed Mediouni
2026-02-26 23:30   ` Alistair Francis
2026-02-26 23:47     ` Conor Dooley
2026-02-27  0:56       ` Alistair Francis
2026-02-27  9:27         ` Thomas Huth
2026-02-27 12:28           ` Djordje Todorovic
2026-02-27 12:42         ` Djordje Todorovic
2026-02-27 12:56           ` Conor Dooley
2026-02-27 14:24             ` Djordje Todorovic
2026-02-27 22:40               ` Philippe Mathieu-Daudé
2026-02-27 12:40     ` Djordje Todorovic

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=aZ7qp05kxbU7diac@redhat.com \
    --to=berrange@redhat.com \
    --cc=Djordje.Todorovic@htecgroup.com \
    --cc=alistair23@gmail.com \
    --cc=cfu@mips.com \
    --cc=dbarboza@ventanamicro.com \
    --cc=marcel.apfelbaum@gmail.com \
    --cc=mst@redhat.com \
    --cc=philmd@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=thuth@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.