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Wed, 25 Feb 2026 12:30:48 +0000 (UTC) Received: from redhat.com (unknown [10.45.225.165]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id A2CE83003D8B; Wed, 25 Feb 2026 12:30:45 +0000 (UTC) Date: Wed, 25 Feb 2026 12:30:42 +0000 From: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= To: Thomas Huth Cc: Djordje Todorovic , "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , "philmd@linaro.org" , "alistair23@gmail.com" Subject: Re: [PATCH v2 01/16] meson: Add BE RISCV targets Message-ID: References: <20260225102016.200654-1-djordje.todorovic@htecgroup.com> <20260225102016.200654-2-djordje.todorovic@htecgroup.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.14 (2025-02-20) X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass client-ip=170.10.129.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.734, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.78, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Feb 25, 2026 at 11:39:50AM +0100, Thomas Huth wrote: > On 25/02/2026 11.20, Djordje Todorovic wrote: > > Add options to compile riscv64be-softmmu and riscv32be-softmmu > > --- > > meson.build | 7 ++++++- > > 1 file changed, 6 insertions(+), 1 deletion(-) > > > > diff --git a/meson.build b/meson.build > > index 8c6c0a9a32..41ad38d184 100644 > > --- a/meson.build > > +++ b/meson.build > > @@ -55,6 +55,11 @@ supported_cpus = ['ppc64', 's390x', 'riscv64', 'x86_64', > > cpu = host_machine.cpu_family() > > +# Unify riscv64be to riscv64. > > +if cpu == 'riscv64be' > > + cpu = 'riscv64' > > +endif > > + > > target_dirs = config_host['TARGET_DIRS'].split() > > # type of binaries to build > > @@ -281,7 +286,7 @@ elif cpu == 'ppc64' > > elif cpu == 'mips64' > > kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu'] > > elif cpu == 'riscv64' > > - kvm_targets = ['riscv64-softmmu'] > > + kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu', 'riscv32be-softmmu', 'riscv64be-softmmu'] > > I really dislike the idea of having yet another target like mips where we > have 4 different flavours (32/64 bits x big/little endian). That increases > the compile- and testing time a lot. Couldn't you do it the ppc64 way? The > ppc64-softmmu target can handle both, big and little endian, no need for a > separate binary here. And we are going the same way with microblaze now - > the microblaze target recently got support for little endian, so we can > finally get rid of the microblazeel target now. Also with the ongoing work to make a single QEMU binary that can support any target, it feels like any problems with handling big and little endian in a single binary will need to be solved regardless, so if practical we should align with that direction from the start. With regards, Daniel -- |: https://berrange.com ~~ https://hachyderm.io/@berrange :| |: https://libvirt.org ~~ https://entangle-photo.org :| |: https://pixelfed.art/berrange ~~ https://fstop138.berrange.com :|