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Wed, 25 Feb 2026 22:55:03 -0800 (PST) Received: from sifive.com ([136.226.240.189]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2adfb5b2268sm13571605ad.6.2026.02.25.22.55.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Feb 2026 22:55:03 -0800 (PST) Date: Thu, 26 Feb 2026 14:55:00 +0800 From: Max Chou To: Richard Henderson Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Aurelien Jarno , Peter Maydell , Alex =?utf-8?Q?Benn=C3=A9e?= Subject: Re: [PATCH 3/3] fpu: Simplify OCP FP8 E4M3 NaN classification in parts_canonicalize Message-ID: References: <20260225110802.1217946-1-max.chou@sifive.com> <20260225110802.1217946-4-max.chou@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=max.chou@sifive.com; helo=mail-pf1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2026-02-26 08:06, Richard Henderson wrote: > On 2/25/26 22:08, Max Chou wrote: > > The OCP FP8 E4M3 format has only a single NaN encoding (0x7F/0xFF), > > Replace the indirect check via parts_is_snan_frac with a direct > > check of no_signaling_nans to make the intent clearer. > > > > Signed-off-by: Max Chou > > --- > > fpu/softfloat-parts.c.inc | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc > > index 3c323c0cec..5ef7e2d921 100644 > > --- a/fpu/softfloat-parts.c.inc > > +++ b/fpu/softfloat-parts.c.inc > > @@ -245,8 +245,8 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status, > > case float_expmax_e4m3: > > if (p->frac_hi == 0b111) { > > frac_shl(p, fmt->frac_shift); > > - p->cls = (parts_is_snan_frac(p->frac_hi, status) > > - ? float_class_snan : float_class_qnan); > > + p->cls = no_signaling_nans(status) ? float_class_qnan : > > + float_class_snan; > > return; > > } > > /* otherwise normal */ > > But parts_is_snan_frac also checks snan_bit_is_one. > > > r~ Hi Richard, You're right. I missed that parts_is_snan_frac respects both snan_bit_is_one and no_signaling_nans flags and I just assumed that user will use no_signaling_nans flag to define the E4M3 NaN. The current implementation correctly allows targets to control E4M3 NaN classification through either mechanism, and this change would have removed the snan_bit_is_one flexibility. I'll drop this patch and send a v2 series containing only the two bug fix patches: Thanks, rnax