From: Lukas Wunner <lukas@wunner.de>
To: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@linux.intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org
Subject: Re: [PATCH v2] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable PME status
Date: Thu, 19 Feb 2026 09:04:30 +0100 [thread overview]
Message-ID: <aZbEDldZxV1KG_5B@wunner.de> (raw)
In-Reply-To: <CAJZ5v0gcZ5vs4WcS0GhvQrG9Kf05LNrNfd+oXz3WDdCA0xGjjw@mail.gmail.com>
On Wed, Feb 18, 2026 at 06:33:15PM +0100, Rafael J. Wysocki wrote:
> First, keeping the ports in D0 may gate runtime PC10. Does it not?
The Root Port in question is on the PCH. I'm not sure, does keeping a
PCH Root Port in D0 also prevent PC10 entry or is that only the case
for Root Ports on the CPU die/tile?
If this does cause a power regression, the pme_is_broken() approach
suggested upthread might be a viable alternative. It'll allow the
Root Port to go to D3hot but will keep interrupts enabled in the
Slot Control register.
Thanks,
Lukas
next prev parent reply other threads:[~2026-02-19 8:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-13 23:14 [PATCH v2] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable PME status Kuppuswamy Sathyanarayanan
2026-02-14 6:01 ` Lukas Wunner
2026-02-14 15:11 ` Lukas Wunner
2026-02-17 17:01 ` Kuppuswamy Sathyanarayanan
2026-02-17 18:22 ` Lukas Wunner
2026-02-18 16:28 ` Kuppuswamy Sathyanarayanan
2026-02-17 16:54 ` Kuppuswamy Sathyanarayanan
2026-02-17 18:08 ` Rafael J. Wysocki
2026-02-18 16:27 ` Kuppuswamy Sathyanarayanan
2026-02-18 17:33 ` Rafael J. Wysocki
2026-02-19 8:04 ` Lukas Wunner [this message]
2026-02-19 11:09 ` Rafael J. Wysocki
2026-02-19 21:54 ` Kuppuswamy Sathyanarayanan
2026-03-09 18:04 ` Kuppuswamy Sathyanarayanan
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