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Mon, 9 Mar 2026 11:41:01 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 9 Mar 2026 11:41:00 -0700 Received: from Asurada-Nvidia (10.127.8.14) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Mon, 9 Mar 2026 11:41:00 -0700 Date: Mon, 9 Mar 2026 11:40:58 -0700 From: Nicolin Chen To: Shameer Kolothum Thodi CC: "eric.auger@redhat.com" , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "clg@redhat.com" , "alex@shazbot.org" , Nathan Chen , Matt Ochs , Jiandi An , Jason Gunthorpe , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , Krishnakant Jaju , "phrdina@redhat.com" Subject: Re: [PATCH v3 15/32] hw/arm/tegra241-cmdqv: Emulate global and VINTF VCMDQ register reads Message-ID: References: <20260226105056.897-1-skolothumtho@nvidia.com> <20260226105056.897-16-skolothumtho@nvidia.com> <1b64d8d1-85d9-4894-8813-d645977aee68@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; 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Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7307 Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=nicolinc@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Mon, Mar 09, 2026 at 11:04:31AM -0700, Shameer Kolothum Thodi wrote: > > > The VI_VCMDQ register ranges are an alias of the global VCMDQ registers > > > and are only meaningful when a VCMDQ is mapped to a VINTF via ioctl > > > IOMMU_HW_QUEUE_ALLOC. > > If the guest detects he can use a single VMCDQs (I guess he can > > introspect this by reading the SMMU_CMDQ_PARAM_0) how does he know if > > he > > shall access your so-called "Global VCMD regs" at 0x10000 or VI0 regs > > (0x30000-40000). How does the guest know that he is supposed to use VI0? > > The CMDQ registers can be accessed via both the so called "Global VCMDQ registers > Page0" and by "VINTF logical VCMDQ registers Page 0". And they are aliased. > > The difference being(from Nicolin's explanation here[0]): > > " > The global page0 is programmable at any time so long as CMDQV_EN > is enabled. > > The logical page0 is programmable only when SW allocates and maps > global vcmdq(s) to a VINTF. "logical" also means "local" to that > VINTF. > ". > > IIUC, for now a Linux Guest kernel will only use "VINTF logical VCMDQ > registers Page 0". Yes. > The question is whether QEMU should also support accesses via the > "Global VCMDQ registers Page 0" if some other guest implementation > chooses to use that path. Yes. The point is that we can't reject guest's access to the global MMIO space. So, QEMU has to support both. But guest OS is allowed to do a partial map/alloc, so global MMIO page isn't identical to the VINTF logical page in this case. In an extreme corner case, guest OS might try to enable a VCMDQ via the global MMIO space, though the vcmdq isn't allocated/mapped to a VINTF. QEMU should still allow these MMIOs but does not essentially make the vcmdq functional, since this would be "unpredictable" in a physical HW situation. Maybe we should elaborate these in the commit message. Nicolin > @Nicolin, please correct me if that assumption is not right.