From: Ravi Bangoria <ravi.bangoria@amd.com>
To: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Jiri Olsa <jolsa@kernel.org>,
Stephane Eranian <eranian@google.com>,
Ian Rogers <irogers@google.com>, Joe Mario <jmario@redhat.com>,
Leo Yan <leo.yan@linaro.org>,
alisaidi@amazon.com, Andi Kleen <ak@linux.intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
dave.hansen@linux.intel.com, "H. Peter Anvin" <hpa@zytor.com>,
Ingo Molnar <mingo@redhat.com>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Borislav Petkov <bp@alien8.de>,
x86@kernel.org,
linux-perf-users <linux-perf-users@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Sandipan Das <sandipan.das@amd.com>,
ananth.narayan@amd.com, Kim Phillips <kim.phillips@amd.com>,
santosh.shukla@amd.com, Ravi Bangoria <ravi.bangoria@amd.com>
Subject: Re: [PATCH v3 02/15] perf/x86/amd: Add IBS OP_DATA2 DataSrc bit definitions
Date: Fri, 30 Sep 2022 10:18:40 +0530 [thread overview]
Message-ID: <aa91fc2d-319c-bbb2-d011-e60f7c04d776@amd.com> (raw)
In-Reply-To: <CAM9d7cjVcGLn+dmajox6ASxx=YQYv9Viv+wzSXdaqCEJrow56w@mail.gmail.com>
On 30-Sep-22 10:11 AM, Namhyung Kim wrote:
> Hi Ravi,
>
> On Wed, Sep 28, 2022 at 2:59 AM Ravi Bangoria <ravi.bangoria@amd.com> wrote:
>>
>> IBS_OP_DATA2 DataSrc provides detail about location of the data
>> being accessed from by load ops. Define macros for legacy and
>> extended DataSrc values.
>>
>> Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
>> ---
>> arch/x86/include/asm/amd-ibs.h | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
>> index f3eb098d63d4..cb2a5e113daa 100644
>> --- a/arch/x86/include/asm/amd-ibs.h
>> +++ b/arch/x86/include/asm/amd-ibs.h
>> @@ -6,6 +6,22 @@
>>
>> #include <asm/msr-index.h>
>>
>> +/* IBS_OP_DATA2 DataSrc */
>> +#define IBS_DATA_SRC_LOC_CACHE 2
>> +#define IBS_DATA_SRC_DRAM 3
>> +#define IBS_DATA_SRC_REM_CACHE 4
>> +#define IBS_DATA_SRC_IO 7
>> +
>> +/* IBS_OP_DATA2 DataSrc Extension */
>> +#define IBS_DATA_SRC_EXT_LOC_CACHE 1
>> +#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE 2
>> +#define IBS_DATA_SRC_EXT_DRAM 3
>> +#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE 5
>
> Is 4 undefined intentionally?
Yes, Here is the snippet from PPR (Processor Programming Reference) doc:
Values | Description
---------------------------------------------------------------------
0h | No valid status.
1h | Local L3 or other L1/L2 in CCX.
2h | Another CCX cache in the same NUMA node.
3h | DRAM.
4h | Reserved.
5h | Another CCX cache in a different NUMA node.
6h | DRAM address map with "long latency" bit set.
7h | MMIO/Config/PCI/APIC.
8h | Extension Memory (S-Link, GenZ, etc - identified by the CS
| target and/or address map at DF's choice).
9h-Bh | Reserved.
Ch | Peer Agent Memory.
Dh-1Fh | Reserved.
Thanks,
Ravi
next prev parent reply other threads:[~2022-09-30 4:52 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-28 9:57 [PATCH v3 00/15] perf mem/c2c: Add support for AMD Ravi Bangoria
2022-09-28 9:57 ` [PATCH v3 01/15] perf/mem: Introduce PERF_MEM_LVLNUM_{EXTN_MEM|IO} Ravi Bangoria
2022-09-30 9:31 ` [tip: perf/core] " tip-bot2 for Ravi Bangoria
2022-09-30 10:48 ` [PATCH v3 01/15] " kajoljain
2022-09-30 12:50 ` Ravi Bangoria
2022-09-30 14:17 ` Liang, Kan
2022-10-01 6:37 ` Ravi Bangoria
2022-10-03 13:15 ` Liang, Kan
2022-10-06 11:38 ` Ravi Bangoria
2022-10-14 13:53 ` Arnaldo Carvalho de Melo
2022-10-14 15:04 ` Ravi Bangoria
2022-10-27 8:25 ` Peter Zijlstra
2022-10-28 6:41 ` [tip: perf/urgent] perf/mem: Rename PERF_MEM_LVLNUM_EXTN_MEM to PERF_MEM_LVLNUM_CXL tip-bot2 for Ravi Bangoria
2022-09-28 9:57 ` [PATCH v3 02/15] perf/x86/amd: Add IBS OP_DATA2 DataSrc bit definitions Ravi Bangoria
2022-09-30 4:41 ` Namhyung Kim
2022-09-30 4:48 ` Ravi Bangoria [this message]
2022-09-30 5:11 ` Namhyung Kim
2022-09-30 6:16 ` Ravi Bangoria
2022-09-30 9:31 ` [tip: perf/core] " tip-bot2 for Ravi Bangoria
2022-09-28 9:57 ` [PATCH v3 03/15] perf/x86/amd: Support PERF_SAMPLE_DATA_SRC Ravi Bangoria
2022-09-30 9:31 ` [tip: perf/core] " tip-bot2 for Ravi Bangoria
2022-09-28 9:57 ` [PATCH v3 04/15] perf/x86/amd: Support PERF_SAMPLE_{WEIGHT|WEIGHT_STRUCT} Ravi Bangoria
2022-09-30 5:09 ` Namhyung Kim
2022-09-30 9:31 ` [tip: perf/core] " tip-bot2 for Ravi Bangoria
2022-09-28 9:57 ` [PATCH v3 05/15] perf/x86/amd: Support PERF_SAMPLE_ADDR Ravi Bangoria
2022-09-30 9:31 ` [tip: perf/core] " tip-bot2 for Ravi Bangoria
2022-09-28 9:57 ` [PATCH v3 06/15] perf/x86/amd: Support PERF_SAMPLE_PHY_ADDR Ravi Bangoria
2022-09-30 4:59 ` Namhyung Kim
2022-09-30 5:05 ` Ravi Bangoria
2022-09-30 9:31 ` [tip: perf/core] " tip-bot2 for Ravi Bangoria
2022-09-30 17:02 ` [PATCH v3 06/15] " Jiri Olsa
2022-09-28 9:57 ` [PATCH v3 07/15] perf/uapi: Define PERF_MEM_SNOOPX_PEER in kernel header file Ravi Bangoria
2022-09-30 9:31 ` [tip: perf/core] " tip-bot2 for Ravi Bangoria
2022-09-28 9:57 ` [PATCH v3 08/15] perf tool: Sync include/uapi/linux/perf_event.h header Ravi Bangoria
2022-09-28 9:57 ` [PATCH v3 09/15] perf tool: Sync arch/x86/include/asm/amd-ibs.h header Ravi Bangoria
2022-09-28 9:58 ` [PATCH v3 10/15] perf mem: Add support for printing PERF_MEM_LVLNUM_{EXTN_MEM|IO} Ravi Bangoria
2022-09-28 9:58 ` [PATCH v3 11/15] perf mem/c2c: Set PERF_SAMPLE_WEIGHT for LOAD_STORE events Ravi Bangoria
2022-09-28 9:58 ` [PATCH v3 12/15] perf mem/c2c: Add load store event mappings for AMD Ravi Bangoria
2022-09-28 9:58 ` [PATCH v3 13/15] perf mem/c2c: Avoid printing empty lines for unsupported events Ravi Bangoria
2022-09-28 9:58 ` [PATCH v3 14/15] perf mem: Use more generic term for LFB Ravi Bangoria
2022-09-28 9:58 ` [PATCH v3 15/15] perf script: Add missing fields in usage hint Ravi Bangoria
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