Re: [PATCH 12/14] include/drm/display/dp: Add DPCD registers for configuring Panel Replay + VRR

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Feb 23, 2026 at 07:14:29PM +0530, Ankit Nautiyal wrote:
> Add additional DPCDs required to be configured to support VRR with Panel
> Replay. These DPCDs are specifically required for configuring Adaptive Sync
> SDP and are introduced in DP v2.1.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  include/drm/display/drm_dp.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index e4eebabab975..e63705415647 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -773,6 +773,15 @@
>  # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)
>  # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)
>  
> +#define PANEL_REPLAY_CONFIG3				0x11a	/* DP 2.1 */
> +# define AS_SDP_SETUP_TIME_MASK				(3 << 6)
> +# define AS_SDP_SETUP_TIME_T1				0
> +# define AS_SDP_SETUP_TIME_DYNAMIC			1	/* uses Table 2-227 */
                                                                        ^^^^^^^^^^^

That reference is likely very DP spec version specific.

> +# define AS_SDP_SETUP_TIME_T2				2

Missing the shift on the values.

> +
> +#define AS_SDP_TRANSMISSION_TIMIING_CONFIG	0x11b	/* DP 2.1 */
> +# define AS_SDP_ONE_LINE_EARLIER_ENABLE		BIT(7)
> +
>  #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
>  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>  #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel