From: Niklas Cassel <cassel@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Cc: jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org,
kwilczynski@kernel.org, bhelgaas@google.com, robh@kernel.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Bjorn Helgaas <helgaas@kernel.org>
Subject: Re: [PATCH 1/2] PCI: dwc: ep: Add MSI Enable checks before raising MSI to the host
Date: Fri, 27 Feb 2026 11:12:27 +0100 [thread overview]
Message-ID: <aaFuC-oJyk7Ka2Ss@ryzen> (raw)
In-Reply-To: <20260225162359.116000-2-manivannan.sadhasivam@oss.qualcomm.com>
On Wed, Feb 25, 2026 at 09:53:58PM +0530, Manivannan Sadhasivam wrote:
> PCIe spec r7, sec 7.7.1.2 mandates that a Function should raise MSI only if
> the MSI Enable bit is set and MSI-X enable bit is clear.
>
> Hence, add those checks to be spec compliant with relevant helpers to avoid
> code duplication.
>
> Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> ---
> .../pci/controller/dwc/pcie-designware-ep.c | 43 ++++++++++++++++---
> 1 file changed, 37 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 295076cf70de..fcbd648e049e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -672,6 +672,17 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> return 0;
> }
>
> +static bool dw_pcie_ep_msi_enabled(struct dw_pcie_ep *ep,
> + struct dw_pcie_ep_func *ep_func, u8 func_no)
> +{
> + u32 val, reg;
> +
> + reg = ep_func->msi_cap + PCI_MSI_FLAGS;
> + val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
Since you are doing a readw, I think it looks a bit weird that val
is u32 instead of u16.
> +
> + return FIELD_GET(PCI_MSI_FLAGS_ENABLE, val);
> +}
> +
> static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
> {
> struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> @@ -682,11 +693,11 @@ static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
> if (!ep_func || !ep_func->msi_cap)
> return -EINVAL;
>
> - reg = ep_func->msi_cap + PCI_MSI_FLAGS;
> - val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
> - if (!(val & PCI_MSI_FLAGS_ENABLE))
> + if (!dw_pcie_ep_msi_enabled(ep, ep_func, func_no))
> return -EINVAL;
>
> + reg = ep_func->msi_cap + PCI_MSI_FLAGS;
> + val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
> val = FIELD_GET(PCI_MSI_FLAGS_QSIZE, val);
>
> return 1 << val;
> @@ -716,6 +727,17 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> return 0;
> }
>
> +static bool dw_pcie_ep_msix_enabled(struct dw_pcie_ep *ep,
> + struct dw_pcie_ep_func *ep_func, u8 func_no)
> +{
> + u32 val, reg;
> +
> + reg = ep_func->msix_cap + PCI_MSIX_FLAGS;
> + val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
Since you are doing a readw, I think it looks a bit weird that val
is u32 instead of u16.
> +
> + return FIELD_GET(PCI_MSIX_FLAGS_ENABLE, val);
> +}
> +
> static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
> {
> struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> @@ -726,11 +748,11 @@ static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
> if (!ep_func || !ep_func->msix_cap)
> return -EINVAL;
>
> - reg = ep_func->msix_cap + PCI_MSIX_FLAGS;
> - val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
> - if (!(val & PCI_MSIX_FLAGS_ENABLE))
> + if (!dw_pcie_ep_msix_enabled(ep, ep_func, func_no))
> return -EINVAL;
>
> + reg = ep_func->msix_cap + PCI_MSIX_FLAGS;
> + val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
> val &= PCI_MSIX_FLAGS_QSIZE;
Since you are touching these lines, I think you should change this to
use FIELD_GET() just like all other functions in this file.
If you don't want to do it in the same patch, then do it in a separate
patch in the same series.
>
> return val + 1;
> @@ -877,6 +899,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
> if (!ep_func || !ep_func->msi_cap)
> return -EINVAL;
>
> + /*
> + * PCIe spec r7, sec 7.7.1.2 mandates that a Function should raise MSI
> + * only if the MSI Enable bit is set and MSI-X Enable bit is clear.
> + */
> + if (!dw_pcie_ep_msi_enabled(ep, ep_func, func_no) ||
> + (dw_pcie_ep_msi_enabled(ep, ep_func, func_no) &&
> + dw_pcie_ep_msix_enabled(ep, ep_func, func_no)))
Here we will call dw_pcie_ep_msi_enabled() twice per dw_pcie_ep_raise_msi_irq().
I would call dw_pcie_ep_msi_enabled() once and store the result in a local
variable, to avoid the latency of doing two reads instead of one, for each
dw_pcie_ep_raise_msi_irq().
Kind regards,
Niklas
next prev parent reply other threads:[~2026-02-27 10:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-25 16:23 [PATCH 0/2] PCI: dwc: ep: MSI/MSI-X checks Manivannan Sadhasivam
2026-02-25 16:23 ` [PATCH 1/2] PCI: dwc: ep: Add MSI Enable checks before raising MSI to the host Manivannan Sadhasivam
2026-02-27 10:12 ` Niklas Cassel [this message]
2026-02-25 16:23 ` [PATCH 2/2] PCI: dwc: ep: Add MSI-X Enable checks before raising MSI-X " Manivannan Sadhasivam
2026-02-27 10:13 ` Niklas Cassel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aaFuC-oJyk7Ka2Ss@ryzen \
--to=cassel@kernel.org \
--cc=bhelgaas@google.com \
--cc=helgaas@kernel.org \
--cc=jingoohan1@gmail.com \
--cc=kwilczynski@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=mani@kernel.org \
--cc=manivannan.sadhasivam@oss.qualcomm.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.