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[104.155.56.206]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bfabb84esm199871075e9.0.2026.02.27.06.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 06:31:50 -0800 (PST) Date: Fri, 27 Feb 2026 14:31:47 +0000 From: Mostafa Saleh To: Tao Tang Cc: Eric Auger , Peter Maydell , "Michael S . Tsirkin" , Marcel Apfelbaum , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Chao Liu Subject: Re: [RFC v4 02/31] hw/arm/smmuv3: Correct SMMUEN field name in CR0 Message-ID: References: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> <20260221100250.2976287-3-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260221100250.2976287-3-tangtao1634@phytium.com.cn> Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=smostafa@google.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Sat, Feb 21, 2026 at 06:02:21PM +0800, Tao Tang wrote: > The FIELD macro for the SMMU enable bit in the CR0 register was > incorrectly named SMMU_ENABLE. > > The ARM SMMUv3 Architecture Specification (both older IHI 0070.E.a and > newer IHI 0070.G.b) consistently refers to the SMMU enable bit as SMMUEN. > > This change makes our implementation consistent with the manual. > > Signed-off-by: Tao Tang > Reviewed-by: Eric Auger > Link: https://lists.nongnu.org/archive/html/qemu-arm/2025-09/msg01270.html Same comment about fixes. Reviewed-by: Mostafa Saleh Thanks, Mostafa > --- > hw/arm/smmuv3-internal.h | 2 +- > include/hw/arm/smmuv3-common.h | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index a6464425ec3..ebdb4ebae67 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -41,7 +41,7 @@ typedef enum SMMUTranslationClass { > > static inline int smmu_enabled(SMMUv3State *s) > { > - return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE); > + return FIELD_EX32(s->cr[0], CR0, SMMUEN); > } > > /* Command Queue Entry */ > diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h > index 2df54ba60f9..9f78bbe89eb 100644 > --- a/include/hw/arm/smmuv3-common.h > +++ b/include/hw/arm/smmuv3-common.h > @@ -351,7 +351,7 @@ REG32(IDR5, 0x14) > REG32(IIDR, 0x18) > REG32(AIDR, 0x1c) > REG32(CR0, 0x20) > - FIELD(CR0, SMMU_ENABLE, 0, 1) > + FIELD(CR0, SMMUEN, 0, 1) > FIELD(CR0, EVENTQEN, 2, 1) > FIELD(CR0, CMDQEN, 3, 1) > > -- > 2.34.1 >