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[104.155.56.206]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4399c75b8afsm7922957f8f.23.2026.02.27.06.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 06:31:08 -0800 (PST) Date: Fri, 27 Feb 2026 14:31:05 +0000 From: Mostafa Saleh To: Tao Tang Cc: Eric Auger , Peter Maydell , "Michael S . Tsirkin" , Marcel Apfelbaum , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Chao Liu Subject: Re: [RFC v4 01/31] hw/arm/smmuv3-common: Fix incorrect reserved mask for SMMU CR0 register Message-ID: References: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> <20260221100250.2976287-2-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260221100250.2976287-2-tangtao1634@phytium.com.cn> Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=smostafa@google.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Sat, Feb 21, 2026 at 06:02:20PM +0800, Tao Tang wrote: > The current definition of the SMMU_CR0_RESERVED mask is incorrect. > It mistakenly treats bit 10 (DPT_WALK_EN) as a reserved bit while > treating bit 9 (RES0) as an implemented bit. > > According to the SMMU architecture specification, the layout for CR0 is: > | 31:11| RES0 | > | 10 | DPT_WALK_EN | > | 9 | RES0 | > | 8:6 | VMW | > | 5 | RES0 | > | 4 | ATSCHK | > | 3 | CMDQEN | > | 2 | EVENTQEN | > | 1 | PRIQEN | > | 0 | SMMUEN | > > Signed-off-by: Tao Tang > Reviewed-by: Eric Auger > Link: https://lists.gnu.org/archive/html/qemu-arm/2025-06/msg00088.html I think fixes as this, should be separate, that would make the series smaller. Reviewed-by: Mostafa Saleh Thanks, Mostafa > --- > include/hw/arm/smmuv3-common.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h > index 67a23fbeaae..2df54ba60f9 100644 > --- a/include/hw/arm/smmuv3-common.h > +++ b/include/hw/arm/smmuv3-common.h > @@ -355,7 +355,7 @@ REG32(CR0, 0x20) > FIELD(CR0, EVENTQEN, 2, 1) > FIELD(CR0, CMDQEN, 3, 1) > > -#define SMMU_CR0_RESERVED 0xFFFFFC20 > +#define SMMU_CR0_RESERVED 0xFFFFFA20 > > REG32(CR0ACK, 0x24) > REG32(CR1, 0x28) > -- > 2.34.1 >