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[104.155.56.206]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4399c76c714sm7803386f8f.39.2026.02.27.06.39.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 06:39:58 -0800 (PST) Date: Fri, 27 Feb 2026 14:39:55 +0000 From: Mostafa Saleh To: Tao Tang Cc: Eric Auger , Peter Maydell , "Michael S . Tsirkin" , Marcel Apfelbaum , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Chao Liu Subject: Re: [RFC v4 09/31] hw/arm/smmuv3: Enforce Secure stage 2 capability check when decoding STE Message-ID: References: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> <20260221100250.2976287-10-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260221100250.2976287-10-tangtao1634@phytium.com.cn> Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=smostafa@google.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Sat, Feb 21, 2026 at 06:02:28PM +0800, Tao Tang wrote: > When decoding a Stream Table Entry (STE) from the Secure stream table > that enables stage-2 translation, verify that the SMMU implementation > advertises Secure stage-2 support via S_IDR1.SEL2. If stage-2 is > requested but S_IDR1.SEL2 is 0, mark the STE as ILLEGAL. > > This implements the requirement from the Arm SMMUv3 architecture > specification (IHI 0070G.b, Section 5.2, Page 218) that a Secure STE > with stage-2 enabled is only valid when the implementation supports > Secure stage-2 translation. > > Signed-off-by: Tao Tang > --- > hw/arm/smmuv3.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 2192bec2368..d011357253e 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -623,6 +623,16 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, > if (ret) { > goto bad_ste; > } > + > + /* > + * Stage 2 is implemented but Secure stage 2 is not supported while > + * STE is from Secure stream table. STE is ILLEGAL in this case > + * according to (IHI 0070G.b) 5.2 STE, Stream Table Entry, Page 218. > + */ > + if ((cfg->sec_sid == SMMU_SEC_SID_S) && > + !(FIELD_EX32(s->bank[SMMU_SEC_SID_S].idr[1], S_IDR1, SEL2))) { > + goto bad_ste; > + } The IDR is not currently set, we can just safely return bad_ste for “SMMU_SEC_SID_S”, no need to complicate things until SEL2 is supported. Thanks, Mostafa > } > > /* Multiple context descriptors require SubstreamID support */ > -- > 2.34.1 >