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[104.155.56.206]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439b6d540b2sm9763731f8f.36.2026.03.02.11.17.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2026 11:17:26 -0800 (PST) Date: Mon, 2 Mar 2026 19:17:23 +0000 From: Mostafa Saleh To: Eric Auger Cc: Tao Tang , Peter Maydell , "Michael S . Tsirkin" , Marcel Apfelbaum , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Chao Liu Subject: Re: [RFC v4 16/31] hw/arm/smmuv3: Plumb SEC_SID through IOMMU notifier path Message-ID: References: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> <20260221101706.2994213-1-tangtao1634@phytium.com.cn> <6a6144fe-3db3-4ce8-8a8c-c1391d7aa550@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <6a6144fe-3db3-4ce8-8a8c-c1391d7aa550@redhat.com> Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=smostafa@google.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Mon, Mar 02, 2026 at 07:26:10PM +0100, Eric Auger wrote: > > > On 2/27/26 3:47 PM, Mostafa Saleh wrote: > > On Sat, Feb 21, 2026 at 06:17:06PM +0800, Tao Tang wrote: > >> Extend IOMMU notifier functions to be SEC_SID-aware, ensuring that > >> invalidation notifications are dispatched to the correct security-aware > >> address space. > >> > >> This ensures IOMMU notifier events (e.g., to VFIO) are correctly routed > >> to the appropriate security world's address space, maintaining isolation > >> between secure and non-secure DMA operations. > > I don’t think that VFIO cares about secure regime, my guess is to > > keep the functions as this and don’t call them for secure invalidations. > > So do we want to prevent VFIO devices from working in secure mode along > with the SMMU? Yes, my impression was that VFIO only works with NS devices, for example I see vfio_iommu_map_notify() only deals with system memory: if (iotlb->target_as != &address_space_memory) { error_setg(&local_err, "Wrong target AS \"%s\", only system memory is allowed", Otherwise, the callback needs to be enlighted by different address spaces, I am not sure how (and what uses cases?) will that be done, does QEMU emulate TZ in that case? (and present some devices as secure?) Thanks, Mostafa > > Eric > > > > Thanks, > > Mostafa > > > >> Signed-off-by: Tao Tang > >> --- > >> hw/arm/smmuv3.c | 18 +++++++++++------- > >> 1 file changed, 11 insertions(+), 7 deletions(-) > >> > >> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > >> index 4a4de719a7c..e33a7babd1c 100644 > >> --- a/hw/arm/smmuv3.c > >> +++ b/hw/arm/smmuv3.c > >> @@ -1195,15 +1195,16 @@ epilogue: > >> * @tg: translation granule (if communicated through range invalidation) > >> * @num_pages: number of @granule sized pages (if tg != 0), otherwise 1 > >> * @stage: Which stage(1 or 2) is used > >> + * @sec_sid: StreamID Security state > >> */ > >> static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, > >> IOMMUNotifier *n, > >> int asid, int vmid, > >> dma_addr_t iova, uint8_t tg, > >> - uint64_t num_pages, int stage) > >> + uint64_t num_pages, int stage, > >> + SMMUSecSID sec_sid) > >> { > >> SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > >> - SMMUSecSID sec_sid = SMMU_SEC_SID_NS; > >> SMMUEventInfo eventinfo = {.sec_sid = sec_sid, > >> .inval_ste_allowed = true}; > >> SMMUTransCfg *cfg = smmuv3_get_config(sdev, &eventinfo, sec_sid); > >> @@ -1251,7 +1252,8 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, > >> } > >> > >> event.type = IOMMU_NOTIFIER_UNMAP; > >> - event.entry.target_as = &address_space_memory; > >> + event.entry.target_as = smmu_get_address_space(sdev->smmu, sec_sid); > >> + g_assert(event.entry.target_as); > >> event.entry.iova = iova; > >> event.entry.addr_mask = num_pages * (1 << granule) - 1; > >> event.entry.perm = IOMMU_NONE; > >> @@ -1262,7 +1264,8 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, > >> /* invalidate an asid/vmid/iova range tuple in all mr's */ > >> static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, int vmid, > >> dma_addr_t iova, uint8_t tg, > >> - uint64_t num_pages, int stage) > >> + uint64_t num_pages, int stage, > >> + SMMUSecSID sec_sid) > >> { > >> SMMUDevice *sdev; > >> > >> @@ -1274,7 +1277,8 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, int vmid, > >> iova, tg, num_pages, stage); > >> > >> IOMMU_NOTIFIER_FOREACH(n, mr) { > >> - smmuv3_notify_iova(mr, n, asid, vmid, iova, tg, num_pages, stage); > >> + smmuv3_notify_iova(mr, n, asid, vmid, iova, tg, > >> + num_pages, stage, sec_sid); > >> } > >> } > >> } > >> @@ -1307,7 +1311,7 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage, > >> if (!tg) { > >> trace_smmuv3_range_inval(sec_sid, vmid, asid, addr, > >> tg, 1, ttl, leaf, stage); > >> - smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, 1, stage); > >> + smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, 1, stage, sec_sid); > >> if (stage == SMMU_STAGE_1) { > >> smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl, sec_sid); > >> } else { > >> @@ -1331,7 +1335,7 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage, > >> trace_smmuv3_range_inval(sec_sid, vmid, asid, addr, tg, > >> num_pages, ttl, leaf, stage); > >> smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, > >> - num_pages, stage); > >> + num_pages, stage, sec_sid); > >> if (stage == SMMU_STAGE_1) { > >> smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, > >> num_pages, ttl, sec_sid); > >> -- > >> 2.34.1 > >> >