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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48868889337sm13769957f8f.34.2026.09.24.02.57.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Sep 2026 02:57:18 -0700 (PDT) Message-ID: Date: Thu, 24 Sep 2026 11:57:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v4 08/25] target/arm/kvm: handle writeback for special ID register fields Content-Language: en-US To: Khushit Shah , qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev Cc: cohuck@redhat.com, peter.maydell@linaro.org, richard.henderson@linaro.org, maz@kernel.org, oliver.upton@linux.dev, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, gshan@redhat.com, skolothumtho@nvidia.com, sebott@redhat.com, armbru@redhat.com, philmd@linaro.org, yangjinqian1@huawei.com, shaju.abraham@nutanix.com, mark.caveayland@nutanix.com, ping@khushitshah.com, sandesh.patel@nutanix.com References: <20260921123249.1708067-1-khushit.shah@nutanix.com> <20260921123249.1708067-9-khushit.shah@nutanix.com> From: Eric Auger In-Reply-To: <20260921123249.1708067-9-khushit.shah@nutanix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/21/26 2:32 PM, Khushit Shah wrote: > Some fields should not be written back to KVM for various reasons: > - ID_AA64PFR0_EL1.GIC / ID_PFR1_EL1.GIC are fabricated by KVM based on > the gic-version property. > - KVM does not allow writing 0 to ID_DFR0_EL1.CopDbg, which breaks > booting an AArch64-only guest on a host that also supports AArch32. > - ID_DFR0_EL1.PerfMon is populated by KVM even for AArch64-only guests > but is not writable there. > - MPIDR_EL1 is managed by KVM based on vCPU index. > - Hold off writing back CLIDR_EL1 until we properly support exposing > cache topology to a KVM guest. > > Signed-off-by: Khushit Shah > --- > target/arm/cpu-idregs.c | 6 ++++++ > target/arm/cpu-idregs.h | 2 ++ > target/arm/kvm.c | 40 +++++++++++++++++++++++++++++++++++++++- > 3 files changed, 47 insertions(+), 1 deletion(-) > > diff --git a/target/arm/cpu-idregs.c b/target/arm/cpu-idregs.c > index d58b8ed063..1f7ebfe9bb 100644 > --- a/target/arm/cpu-idregs.c > +++ b/target/arm/cpu-idregs.c > @@ -107,3 +107,9 @@ bool arm_field_is_writable(const ARM64SysRegField *field) > return (arm64_id_regs[field->index].writable_mask & field_mask) > == field_mask; > } > + > +bool field_matches(const ARM64SysRegField *field, ARMIDRegisterIdx index, > + const char *name) > +{ > + return field->index == index && !strcmp(field->name, name); > +} > diff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h > index aab1a79db1..8ef3f9350e 100644 > --- a/target/arm/cpu-idregs.h > +++ b/target/arm/cpu-idregs.h > @@ -35,4 +35,6 @@ extern ARM64SysReg arm64_id_regs[NUM_ID_IDX]; > > uint64_t arm_get_field_mask(const ARM64SysRegField *field); > bool arm_field_is_writable(const ARM64SysRegField *field); > +bool field_matches(const ARM64SysRegField *field, ARMIDRegisterIdx index, > + const char *name); > #endif > diff --git a/target/arm/kvm.c b/target/arm/kvm.c > index 2d94b3a884..70d9a07580 100644 > --- a/target/arm/kvm.c > +++ b/target/arm/kvm.c > @@ -1317,10 +1317,40 @@ bool kvm_arm_cpu_post_load(ARMCPU *cpu) > return true; > } > > +static bool arm_field_skip_writeback_always(const ARM64SysRegField *field) > +{ > + /* > + * GIC is controlled by the gic-version property and fabricated by KVM > + * when the vGIC device is created, so a named CPU model must not touch > + * it. KVM also rejects writing 0 to ID_DFR0_EL1.CopDbg, which breaks > + * booting a model that lacks AArch32 support on a host that supports > + * it. MPIDR_EL1 is managed by KVM based on vCPU index, skip writing it > + * back. Similarly, skip writing back CLIDR_EL1 till we properly > + * support exposing cache for KVM guest. > + */ > + return field_matches(field, ID_AA64PFR0_EL1_IDX, "GIC") > + || field_matches(field, ID_PFR1_EL1_IDX, "GIC") > + || field_matches(field, ID_DFR0_EL1_IDX, "CopDbg") > + || field->index == MPIDR_EL1_IDX > + || field->index == CLIDR_EL1_IDX; what does happen for SMIDR_EL1 and GMID_EL1 whose value could not be initialized from host. The setter for any of their field shall fail. > +} > + > +static bool > +arm_field_skip_writeback_if_not_writable(const ARM64SysRegField *field) > +{ > + /* > + * KVM populates ID_DFR0_EL1.PerfMon even for AArch64-only guests but > + * does not expose it as writable there, so skip it when it is not > + * writable. > + */ > + return field_matches(field, ID_DFR0_EL1_IDX, "PerfMon"); > +} > + > /* > * Copy writable ID reg fields from isar.idregs[] into the KVM cpreg list, > * so the subsequent write_list_to_kvmstate() pushes them to KVM. > - * Only writable fields are copied. > + * Only writable fields are copied; fields that must not be written back > + * (see arm_field_skip_writeback_*) are skipped. > * Returns -1 if any vCPU's ID reg value differs from the host value and the > * field is not writable. > */ > @@ -1357,6 +1387,14 @@ static int kvm_arm_write_idregs_to_cpreg_list(ARMCPU *cpu) > continue; > } > > + if (arm_field_skip_writeback_always(field) || > + (!arm_field_is_writable(field) && > + arm_field_skip_writeback_if_not_writable(field))) { > + /* Never write this field back; keep KVM's value. */ > + writable_mask &= ~field_mask; > + continue; > + } > + > if (!arm_field_is_writable(field)) { > error_report("%s.%s is not writable: host=0x%" PRIx64 > ", requested=0x%" PRIx64, v9 has changed the way new field values are stored. writable field props and non writable field props could have different setters. A non writable field setter just needs to check the new value is the same as the current host value. No need to record the new value in the hashtable for further commitment. Eric