From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D6ABC001DC for ; Fri, 16 Jun 2023 09:40:38 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 523D38621E; Fri, 16 Jun 2023 11:40:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 588A18622D; Fri, 16 Jun 2023 11:40:34 +0200 (CEST) Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by phobos.denx.de (Postfix) with ESMTP id A0B678620D for ; Fri, 16 Jun 2023 11:40:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=minda.chen@starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 721777F8A; Fri, 16 Jun 2023 17:40:25 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 16 Jun 2023 17:34:15 +0800 Received: from [192.168.125.127] (113.72.145.34) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 16 Jun 2023 17:34:14 +0800 Message-ID: Date: Fri, 16 Jun 2023 17:34:12 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v6 0/3] Add StarFive JH7110 PCIe drvier support Content-Language: en-US To: Leo Liang CC: Rick Chen , , Mason Huo , Leyfoon Tan , Kevin Xie References: <20230509082617.119018-1-minda.chen@starfivetech.com> From: Minda Chen In-Reply-To: Content-Type: text/plain; charset="UTF-8" X-Originating-IP: [113.72.145.34] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 2023/6/16 16:42, Leo Liang wrote: > Hi Minda, >=20 > On Thu, Jun 01, 2023 at 09:07:14AM +0800, Minda Chen wrote: >>=20 >> Hi Rick and Leo >> Could you review these series patches? Thanks. >> Since patch 1 was acked by Pali=EF=BC=8C Does it mean patch 1 is accep= ted=EF=BC=9F=20 >=20 > I think acked-by means that the patch is considered good enough to be m= erged. >=20 > Aside from that, your patchset caused CI error by enabling the RTL8169 = driver. > Could you take a look at it ? (https://source.denx.de/u-boot/custodians= /u-boot-riscv/-/jobs/638021) > It's mostly compilation warnings that are being treated as errors. > The patchset looks good to me, I could merge the patchset as soon as th= e CI errors are fixed! >=20 > Thanks & best regards, > Leo >=20 Thanks. I will commit another patch to fix the warning. =20 >> On 2023/5/9 16:26, Minda Chen wrote: >> > These PCIe series patches are based on the JH7110 RISC-V SoC and Vis= ionFive V2 board. >> >=20 >> > The PCIe driver depends on gpio, pinctrl, clk and reset driver to do= init. >> > The PCIe dts configuation includes all these setting. >> >=20 >> > The PCIe drivers codes has been tested on the VisionFive V2 boards. >> > The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet ada= pter. >> >=20 >> > previous patch version >> >=20 >> > v1: https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.= 15180-1-minda.chen@starfivetech.com/ >> > v2: https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.= 95730-1-minda.chen@starfivetech.com/ >> > v3: https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.= 10724-1-minda.chen@starfivetech.com/ >> > v4: https://patchwork.ozlabs.org/project/uboot/cover/20230411010209.= 76561-1-minda.chen@starfivetech.com/ >> > v5: https://patchwork.ozlabs.org/project/uboot/cover/20230423105859.= 125764-1-minda.chen@starfivetech.com/ >> >=20 >> > changes >> > v6 >> > patch 2 >> > 1. Change one VisionFive2 config file. >> > patch 3 >> > 1. remove the pcie interrupt-controller. interrupts setting reve= rt to origin. >> >=20 >> > setting. >> > v5 >> > patch 1 >> > 1. split PLDA controller driver codes to pcie_plda_common.c >> > 2. correct the codes of record secondary number.=20 >> > patch 3 >> > 1. change the pcie dtsi config. make them the same with kernel. >> > =20 >> > v4 >> > patch 1 >> > 1. Remove the IDS_REVISION_ID macros. >> > 2. Replace sec_busno to first_busno in starfive_pcie >> > 3. Remove starfive_pcie_off_conf function. >> > 4. Replace "imply" to "depends on" in PCIe Kconfig. >> > 5 .Check sec_busno in starfive_pcie_addr_valid. >> > =20 >> > v3 >> > patch 1 >> > 1. remove the read vendor ID delay >> > 2. remove starfive_pcie_hide_rc_bar function. do not hide host >> > bridge BAR write. >> > 3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros= . >> > 4. Add comments for bus and address limitation reason in functio= n >> > starfive_pcie_addr_valid >> > 5. Change the multiple line comments in Line 373 >> > 6. Using gpio_request_by_name to get PCIe reset gpio,and using >> > dm_gpio_set_value set GPIO value. >> > patch 2 >> > 1. support PCIeboth 12a and 13b vf2 board. =20 >> > patch 3 >> > 1. reset dts change to reset-gpio. >> >=20 >> > v2 >> > 1. remove clock commit. The pcie clocks change has been includede= d in [1]. >> > 2. Using GENMASK marco1 in patch1. >> > 3. remove the syscon dts node in patch3. The syscon dts dts node = has been >> > included in [1].=20 >> >=20 >> >=20 >> > Mason Huo (3): >> > starfive: pci: Add StarFive JH7110 pcie driver >> > configs: starfive-jh7110: Add support for PCIe host driver >> > riscv: dts: starfive: Enable PCIe host controller >> >=20 >> > .../dts/jh7110-starfive-visionfive-2.dtsi | 11 + >> > arch/riscv/dts/jh7110.dtsi | 74 ++++ >> > configs/starfive_visionfive2_defconfig | 10 + >> > drivers/pci/Kconfig | 13 + >> > drivers/pci/Makefile | 2 + >> > drivers/pci/pcie_plda_common.c | 116 +++++++ >> > drivers/pci/pcie_plda_common.h | 118 +++++++ >> > drivers/pci/pcie_starfive_jh7110.c | 317 +++++++++++++++= +++ >> > 8 files changed, 661 insertions(+) >> > create mode 100644 drivers/pci/pcie_plda_common.c >> > create mode 100644 drivers/pci/pcie_plda_common.h >> > create mode 100644 drivers/pci/pcie_starfive_jh7110.c >> >=20 >> >=20 >> > base-commit: c9c2c95d4cd27fe0cd41fe13a863899d268f973c