From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6077E33C186 for ; Wed, 4 Mar 2026 15:53:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772639594; cv=none; b=KDIJRT+45nTn+DxZaa4o5ew9PiDAiiESUdbsjx7EA80Qgpi24tpo/Rin6zAY8aPycsP12+k36MyWwStaiUSbltoOu0qpc+XMdJxe81OxgT2T+JssZL/FNpfYNyCreHgG//0SQao/6jhSHKs0IrJwGwC/Nb7cnUNHJ8tMhOyNz4I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772639594; c=relaxed/simple; bh=r6s+CcxbWXRLqVcKE/AIUYaryKZMa3LS1CdJjokd8mA=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition; b=HgF7su7b9LOrt5tm19HfHlScMRTcbeup69vnz3o4PSqjdj16hEwRLXxGoQJ99yYQYX+zedjVTxRU4EGqAetMy4FSKF0coVTNMP6Kgcm5VTpJwIEiu6UzfaPU1rljI0ZgJfSk9oBe+9+uFoHg5l/JqTseS2ezbiyVcPd3LwZY8lc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l+MU3/9p; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l+MU3/9p" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 95847C4CEF7; Wed, 4 Mar 2026 15:53:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772639594; bh=r6s+CcxbWXRLqVcKE/AIUYaryKZMa3LS1CdJjokd8mA=; h=Date:From:To:Cc:Subject:From; b=l+MU3/9pJ980jXzvFIJ3QGq9sNL1F7SZCBB0pqmkvDGYZL9VRoJJHsmYyzLj3OGua cByEHZ7rYf6rAtiLrjdkxOk9vnyBKs4MyPMJb9kTYkoksUPlQrclIjADf8spuzTmvW TlF13k3KDCiea2xEP9eaGRX9y1kj/FcduVBg/czE0+roZm3ukT1Vxv63Jpd28JysN0 p4sPpco2h7pht8VkhIJl3XeMiYeoZgGJEnHbd/xmBIDsaCp42Z7XQn5/BHH3QfNZ9L vxFllGnzoDKSV0IgTLzlp77tBQ8UJXeN/CTzPYS/SkI6PYqFW90Q3ShcAFrh1yUX7w 7Pqivw2dN/VvA== Date: Wed, 4 Mar 2026 12:53:10 -0300 From: Arnaldo Carvalho de Melo To: linux-kernel@vger.kernel.org Cc: Amit Shah , Dave Hansen , "H. Peter Anvin" , Sean Christopherson , Zhao Liu , Adrian Hunter , Ian Rogers , James Clark , Jiri Olsa , Namhyung Kim Subject: [PATCH 1/1 fyi] tools headers x86 cpufeatures: Sync with the kernel sources Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline tldr; Just FYI, I'm carrying this on the perf tools tree. Full explanation: There used to be no copies, with tools/ code using kernel headers directly. From time to time tools/perf/ broke due to legitimate kernel hacking. At some point Linus complained about such direct usage. Then we adopted the current model. See further details at: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/include/uapi/README To pick the changes from: f24ef0093dd8cf60 ("KVM: x86: Advertise MOVRS CPUID to userspace") f49ecf5e110ab0ed ("x86/cpufeature: Replace X86_FEATURE_SYSENTER32 with X86_FEATURE_SYSFAST32") db5e82496492b489 ("KVM: SVM: Virtualize and advertise support for ERAPS") This causes these perf files to be rebuilt and brings some X86_FEATURE that may be used by: CC /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o CC /tmp/build/perf/bench/mem-memset-x86-64-asm.o And addresses this perf build warning: Warning: Kernel ABI header differences: diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h Please see tools/include/uapi/README for further details. Cc: Amit Shah Cc: Dave Hansen Cc: H. Peter Anvin Cc: Sean Christopherson Cc: Zhao Liu Signed-off-by: Arnaldo Carvalho de Melo --- tools/arch/x86/include/asm/cpufeatures.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index c3b53beb130078ca..dbe104df339b8c4d 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -84,7 +84,7 @@ #define X86_FEATURE_PEBS ( 3*32+12) /* "pebs" Precise-Event Based Sampling */ #define X86_FEATURE_BTS ( 3*32+13) /* "bts" Branch Trace Store */ #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* syscall in IA32 userspace */ -#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* sysenter in IA32 userspace */ +#define X86_FEATURE_SYSFAST32 ( 3*32+15) /* sysenter/syscall in IA32 userspace */ #define X86_FEATURE_REP_GOOD ( 3*32+16) /* "rep_good" REP microcode works well */ #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* "amd_lbr_v2" AMD Last Branch Record Extension Version 2 */ #define X86_FEATURE_CLEAR_CPU_BUF ( 3*32+18) /* Clear CPU buffers using VERW */ @@ -326,6 +326,7 @@ #define X86_FEATURE_AMX_FP16 (12*32+21) /* AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* Support for VPMADD52[H,L]UQ */ #define X86_FEATURE_LAM (12*32+26) /* "lam" Linear Address Masking */ +#define X86_FEATURE_MOVRS (12*32+31) /* MOVRS instructions */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ @@ -472,6 +473,7 @@ #define X86_FEATURE_GP_ON_USER_CPUID (20*32+17) /* User CPUID faulting */ #define X86_FEATURE_PREFETCHI (20*32+20) /* Prefetch Data/Instruction to Cache Level */ +#define X86_FEATURE_ERAPS (20*32+24) /* Enhanced Return Address Predictor Security */ #define X86_FEATURE_SBPB (20*32+27) /* Selective Branch Prediction Barrier */ #define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */ #define X86_FEATURE_SRSO_NO (20*32+29) /* CPU is not affected by SRSO */ -- 2.53.0