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From: Piotr Jaroszynski <pjaroszynski@nvidia.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ryan Roberts <ryan.roberts@arm.com>,
	Will Deacon <will@kernel.org>,
	 linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org,
	Alistair Popple <apopple@nvidia.com>,
	 Jason Gunthorpe <jgg@nvidia.com>,
	John Hubbard <jhubbard@nvidia.com>, Zi Yan <ziy@nvidia.com>,
	 Breno Leitao <leitao@debian.org>,
	stable@vger.kernel.org
Subject: Re: [PATCH] arm64: contpte: fix set_access_flags() no-op check for SMMU/ATS faults
Date: Thu, 5 Mar 2026 14:49:43 -0800	[thread overview]
Message-ID: <aaoHSV-dL8ernMLR@box> (raw)
In-Reply-To: <aam-ZSHWrkYX8spV@arm.com>

On Thu, Mar 05, 2026 at 05:33:25PM +0000, Catalin Marinas wrote:
> Looking at the patch again, some more comments.
> 
> On Mon, Mar 02, 2026 at 10:37:51PM -0800, Piotr Jaroszynski wrote:
> > diff --git a/arch/arm64/mm/contpte.c b/arch/arm64/mm/contpte.c
> > index bcac4f55f9c1..9868bfe4607c 100644
> > --- a/arch/arm64/mm/contpte.c
> > +++ b/arch/arm64/mm/contpte.c
> > @@ -390,6 +390,23 @@ void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma,
> >  }
> >  EXPORT_SYMBOL_GPL(contpte_clear_young_dirty_ptes);
> >  
> > +static bool contpte_all_subptes_match_access_flags(pte_t *ptep, pte_t entry)
> 
> More of a nitpick: since this checks both the flags and write
> permission, I'd rename to something else. Maybe contpte_ptep_same() to
> somewhat resemble pte_same() used by __ptep_set_access_flags().

pte_same() also compares the PFN though. I picked the _access_flags
suffix to match the ptep_set_access_flags() naming. I do agree the
aliasing of AF and "access flags" is unfortunate, but it seems
preexisting. I am updating the comments to be clearer in v2, let me know
if that works.

> 
> > +{
> > +	pte_t *cont_ptep = contpte_align_down(ptep);
> > +	const pteval_t access_mask = PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY;
> 
> We can drop the PTE_DIRTY from the mask as it's not relevant to the
> hardware permission. It probably doesn't matter in practice.

I think it's good to be consistent and just update everything while we
are doing it such that the sub-PTEs are in sync.

> 
> > +	pteval_t entry_access = pte_val(entry) & access_mask;
> > +	int i;
> > +
> > +	for (i = 0; i < CONT_PTES; i++) {
> > +		pteval_t pte_access = pte_val(__ptep_get(cont_ptep + i)) & access_mask;
> > +
> > +		if (pte_access != entry_access)
> > +			return false;
> > +	}
> > +
> > +	return true;
> > +}
> > +
> >  int contpte_ptep_set_access_flags(struct vm_area_struct *vma,
> >  					unsigned long addr, pte_t *ptep,
> >  					pte_t entry, int dirty)
> > @@ -399,13 +416,35 @@ int contpte_ptep_set_access_flags(struct vm_area_struct *vma,
> >  	int i;
> >  
> >  	/*
> > -	 * Gather the access/dirty bits for the contiguous range. If nothing has
> > -	 * changed, its a noop.
> > +	 * Check whether all sub-PTEs in the CONT block already have the
> > +	 * requested access flags, using raw per-PTE values rather than the
> > +	 * gathered ptep_get() view.
> 
> It's not just about the access flag but AF, dirty and write permission,
> all can be changed by this function (and only to a more permissive
> setting).

Thanks, updating the wording in v2.

> 
> > +	 *
> > +	 * ptep_get() gathers AF/dirty state across the whole CONT block,
> > +	 * which is correct for CPU TLB semantics: with FEAT_HAFDBS the
> > +	 * hardware may set AF/dirty on any sub-PTE and the CPU TLB treats
> > +	 * the gathered result as authoritative for the entire range. But an
> > +	 * SMMU without HTTU (or with HA/HD disabled in CD.TCR) evaluates
> 
> Or CPU equally, we don't force all CPUs in a system to support DBM.

Thanks, updating the wording in v2.

> 
> > +	 * each descriptor individually and will keep faulting on the target
> > +	 * sub-PTE if its flags haven't actually been updated. Gathering can
> > +	 * therefore cause false no-ops when only a sibling has been updated:
> > +	 *  - write faults: target still has PTE_RDONLY (needs PTE_RDONLY cleared)
> > +	 *  - read faults:  target still lacks PTE_AF
> > +	 *
> > +	 * Per Arm ARM (DDI 0487) D8.7.1, any sub-PTE in a CONT range may
> > +	 * become the effective cached translation, so all entries must have
> > +	 * consistent attributes. Check the full CONT block before returning
> > +	 * no-op, and when any sub-PTE mismatches, proceed to update the whole
> > +	 * range.
> >  	 */
> > -	orig_pte = pte_mknoncont(ptep_get(ptep));
> > -	if (pte_val(orig_pte) == pte_val(entry))
> > +	if (contpte_all_subptes_match_access_flags(ptep, entry))
> >  		return 0;
> >  
> > +	/*
> > +	 * Use raw target pte (not gathered) for write-bit unfold decision.
> > +	 */
> > +	orig_pte = pte_mknoncont(__ptep_get(ptep));
> 
> This is fine since all should have the same PTE_WRITE bit.
> 
> Anyway, nothing major, so:
> 
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

Thanks!


      reply	other threads:[~2026-03-05 22:50 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-03  6:37 [PATCH] arm64: contpte: fix set_access_flags() no-op check for SMMU/ATS faults Piotr Jaroszynski
2026-03-03  7:19 ` James Houghton
2026-03-03 12:45   ` Jason Gunthorpe
2026-03-03 21:40   ` Piotr Jaroszynski
2026-03-05  4:31     ` James Houghton
2026-03-03  8:38 ` Ryan Roberts
2026-03-03 18:40   ` Piotr Jaroszynski
2026-03-03 19:12     ` Jason Gunthorpe
2026-03-04 12:20       ` Ryan Roberts
2026-03-04 13:44         ` Jason Gunthorpe
2026-03-04 11:17 ` Catalin Marinas
2026-03-04 13:43   ` Jason Gunthorpe
2026-03-04 15:01     ` Catalin Marinas
2026-03-04 15:39       ` Jason Gunthorpe
2026-03-04 17:16         ` Piotr Jaroszynski
2026-03-04 17:25         ` Catalin Marinas
2026-03-04 17:37 ` Breno Leitao
2026-03-05 17:33 ` Catalin Marinas
2026-03-05 22:49   ` Piotr Jaroszynski [this message]

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