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Thu, 12 Mar 2026 04:16:20 -0700 (PDT) Received: from sifive.com ([136.226.240.165]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c73cdf204afsm5058326a12.10.2026.03.12.04.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 04:16:19 -0700 (PDT) Date: Thu, 12 Mar 2026 19:16:08 +0800 From: Max Chou To: Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Subject: Re: [PATCH v5 0/9] Add Zvfbfa extension support Message-ID: References: <20260306071105.3328365-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=max.chou@sifive.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2026-03-09 14:51, Alistair Francis wrote: > On Fri, Mar 6, 2026 at 5:13 PM Max Chou wrote: > > > > This patch series adds support for the RISC-V Zvfbfa extension, which > > provides additional BF16 vector compute support. > > > > The isa spec of Zvfbfa extension is not ratified yet, so this patch > > series is based on the latest draft of the spec (v0.1) and make the > > Zvfbfa extension as an experimental extension. > > It's not only not ratified, there isn't even a draft spec. A personal > GitHub repo without any tags or releases is not enough for us to take > this unfortunately. > > > > > The Zvfbfa extension adds a 1-bit field, altfmt, to the vtype CSR in > > bit position 8. > > The Zvfbfa extension requires the Zve32f and Zfbfmin extensions. > > > > Specification: > > https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc > > Overall this looks ok. Once a draft spec is released we can apply it > > Alistair > Hi Alistair, Thanks for the review. You asked for a pointer to the standalone ISA spec repo for Zvfbfa — I want to explain why that doesn’t exist and where the spec lives instead. RVIA changed the ISA development workflow: new ISA specifications are no longer developed in standalone repositories. Instead, they are developed as forked branches of the base ISA manual repo (riscv/riscv-isa-manual) and merged into it upon ratification [1]. For Zvfbfa specifically, the official spec artifact under this new workflow is a PR against riscv-isa-manual [2], incorporating the spec text [3]. The PR notes that the spec has passed internal review and ARC review, as documented in the tech-unprivileged list thread [4]. PR #2743 is currently open, meaning ratification is pending but not yet complete. Under the new workflow, merge into main of riscv-isa-manual is the signal that ratification is finalized. If you prefer to wait until that merge happens before applying this patchset, I completely understand. Alternatively, if you are comfortable accepting it as ratification-pending, I am happy to address any remaining technical comments. Please let me know how you would like to proceed. References: [1] https://lists.riscv.org/g/sig-documentation/message/275 [2] https://github.com/riscv/riscv-isa-manual/pull/2743 [3] https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc [4] https://lists.riscv.org/g/tech-unprivileged/message/1031 https://lists.riscv.org/g/tech-unprivileged/message/1085 https://lists.riscv.org/g/tech-unprivileged/message/1109 Best regards, rnax